Senior Principal Analog Design Engineer
Senior Principal Analog Design Engineer
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1 Vacancy
Job Description
About Marvell
Marvells semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise cloud and AI automotive and carrier architectures our innovative technology is enabling new possibilities.
At Marvell you can affect the arc of individual lives lift the trajectory of entire industries and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation above and beyond fleeting trends Marvell is a place to thrive learn and lead.
Your Team Your Impact
As a Senior Principal Analog Design Engineer with Marvell youll be a lead member of the Central Engineering business group. Central Engineering organization provides most advanced and key analog IPs to all businesses within Marvell: including Data Center Networking connectivity.Youll be part of a key analog team that makes an outsized impact not only the organization but also to the technological arc of innovation in the field of high speed electrical/optical links.
What You Can Expect
As a Sr. Principal Analog circuit design engineer you will be collaborating with system architects and a global team of circuit and physical designers to build best in class serial links for various applications and space. Your work would swing between research and development geared towards circuits at bleeding edge of technology and data rates to handson (rollupthe sleeve) design of key analog circuits such as PLL DLLs ADCs DACs CTLE/Filters TX RX CDRs etc.
What Were Looking For
- Completed a MS in Electrical Engineering with 12 years of related experience or PhD degree in Electrical Engineering with 10 years of related experience.
- Expertise in one or more of the following focus areas of analog design: ADC/DACs FrontEnds CTLE PLL Timing circuits CDRs SerDes.
- Ability to collaborate with various other design and functional teams: Layout/ Physical design System architecture Digital design and Validation for the successful development release and support of complex mixed signal IPs
- Strong knowledge on the deep submicron CMOS technologies. Keen eye for analog layout in latest deep submicron technologies and supervision of the same to get the key performance for highspeed design
- Excellent problem solving and analytical skills to take on circuit design challenges.
- Excellent debug skills to drive test plans and support validation for full cycle development of IPs and products
Expected Base Pay Range (USD)
$ per annumThe successful candidates starting base pay will be determined based on jobrelated skills experience qualifications work location and market conditions. The expected base pay range for this role may be modified based on market conditions.
Additional Compensation and Benefit Elements
At Marvell we offer a total compensation package with a base bonus and equity.Health and financial wellbeing are part of the package. That means flexible time off 401k plus a yearend shutdown floating holidays paid time off to volunteer. Have a question about our benefits packages health or financial Ask your recruiter during the interview process.All qualified applicants will receive consideration for employment without regard to race color religion sex national origin sexual orientation gender identity disability or protected veteran status.
Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at .
#LITD1Required Experience:
Staff IC
Employment Type
Full Time
