Sr ASIC Design Engineer
Sr ASIC Design Engineer
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Job Description
Were growing! Our team in Parma (Italy) is seeking a Sr. ASIC Design Engineer.
Responsibilities:
Developing microarchitecture specifications for a next generation Computer Vision processor;
Designing and implementing video compression logic image processing logic and computer vision processors in Verilog and SystemVerilog;
Design integration logic synthesis and design optimization for timing area and power;
Developing frontend methodologies and tool flows;
Participating in chip bringup and testing;
Requirements:
Masters degree in Electrical Engineering with 04 years of experience;
Very Good understanding of Computer architecture Microprocessor Digital electronics VLSI/ASIC design and Logic design;
Good knowledge and experience in using hardware description languages like Verilog/SystemVerilog;
Ability to program in scripting languages like Python and Perl;
Knowledge of design verification and functional coverage;
Strong communication skills and a good team player;
Knowledge is logic synthesis and timing closure are must and some experience is a plus;
Knowledge and/or experience in the areas of Image/Video processing computer vision machine learning are plus;
To apply please submit resume with subject: JOB#VLSI to or apply online on Ambarella website.
As an Equal Opportunity/Affirmative Action Employer Vislab and Ambarella recruit qualified applicants without regard to race color national origin sex physical disability or veteran status.
Please find at this link our privacy disclaimer dedicated to candidates data accordingly to the GDPR: https://tinyurl/yd66nbsa
Required Experience:
Senior IC
Employment Type
Full-Time
