Senior FPGA Emulation Manager 179161

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Senior Emulation & Prototyping Manager

THE ROLE:

The AECG Emulation Team is looking for an experienced handson technical manager to lead a dynamic team of 4 to 6 persons. Our team is responsible for creating emulation environments for pretapeout and postsilicon validation of our most advanced FPGA devices. We use both commercial emulation and prototyping systems and custom hardware solutions to emulate new IP blocks and subsystems including the Processing Subsystem (PS) AI Engine (AIE) and Video Codec Unit (VCU). Work with architecture design verification and embedded software teams to develop plans to verify silicon designs and enable early software development. Create novel solutions around FPGA prototyping and emulation.

THE PERSON:

We are looking for an individual that takes the initiative in developing plans and successfully executing them. The ideal candidate is an innovative problem solver who is adept at driving issues to closure. The person collaborates well with other teams both internal and external to the company and can generate consensus.

KEY RESPONSIBILITIES:

• Manage a hardware team in San Jose and interface with the manager of a team in India.
• Develop project plans track progress and manage resources dependencies and risks.
• Collaborate with global teams to define deliverables and ensure the quality of our FPGAs.
• Work with EDA vendors and external contractors to develop solutions and resolve issues.
• Improve internal processes and ensure compliance with industry standards and best practices.
• Actively contribute to project planning and design reviews for FPGA product families.
• Provide technical coaching career development and performance feedback.

PREFERRED EXPERIENCE:

• Experience managing a small team.
• Strong verbal and written skills run meetings and follow up on action items.
• Strong project management skills arranging resources and managing multiple projects.
• Ideal candidate would have the following:
• Have worked with emulation and prototyping solutions from leading vendors (Synopsys Cadence Siemens) to debug issues and deploy new capabilities including speed adaptors virtual models.
• Experience with Verilog / VHDL.
• Experience implementing and debugging FPGA designs.
• Experience with HDL simulation synthesis and timing closure.
• Knowledge of C programming.
• Knowledge of verification methodologies.
• Knowledge of highspeed interfaces such as PCIe USB Ethernet DDR4/5 LPDDR4/5.
• Knowledge of ARM AXI protocol.
• Experience with embedded processors such as ARM Cortex A53 A72 Microblaze.
• Knowledge of other devices/standards such as SPI IIC SD QSPI OSPI.
• Knowledge of AI/ML video processing networking solutions.

ACADEMIC CREDENTIALS:

• BS / MS (Computer Engineering Electrical Engineering or related equivalent)

LOCATION:

San Jose CA

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Requisition Number:179161
Country:United StatesState:CaliforniaCity:San Jose
Job Function:Design

Benefits offered are described here.

AMD does not accept unsolicited resumes from headhunters recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age ancestry color marital status medical condition mental or physical disability national origin race religion political and/or third party affiliation sex pregnancy sexual orientation gender identity military or veteran status. Please click here for more information.