Standard Cell Layout Engineer
Standard Cell Layout Engineer
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Job Description
Title: Standard Cell Layout Design
About GLOBALFOUNDRIES
GLOBALFOUNDRIES is a leading fullservice semiconductor foundry providing a unique combination of design development and fabrication services to some of the worlds most inspired technology companies. With a global manufacturing footprint spanning three continents GLOBALFOUNDRIES makes possible the technologies and systems that transform industries and give customers the power to shape their markets. For more information visit www.gf.com.
Introduction
In this position you will be integrated in our Foundry IP Development team in Bangalore. In close collaboration with other disciplines across our worldwide engineering teams you will be developing layout for Std cell IP which enable our customers to perform product designs at highest quality standards based on Globalfoundries advanced process nodes.
Job Responsibilities
The development of product grade Standard Cell IP covering the following phases:
Layout Design of Standard Cell IPs
Layout checks like LVS DRC DFM EMIR
Review of Layouts and extend help for other Layout teams
Design Kit prep from layout side verification and validation
Layout automation and script support
Being a good team player taking key initiatives for productivity improvements and innovation
Sign off and release into dedicated IP validation test chips
Specification and documentation
Support of silicon bring up and characterization
Required Qualifications:
Bachelors degree with 10 years or masters degree with 8 years experience in semiconductors/Microelectronics/VLSI engineering.
Practical experiences in Standard Cell layout design in one or several of the following areas:
Layout design and optimization of Combinational and Sequential Cells for various drive strengths and topology options.
Layout design of Power Management Kit cells like Level Shifter Power Gating Isolation and Alwayson Cells.
Layout Architecture design for Ultra High Density and HighPerformance Libraries.
Layout design of custom cells to meet specific low power or highspeed design requirements.
Proficient in handling EDA tools from Synopsis Mentor and Cadence used for layout design like schematic/layout editor parasitic extraction tools DRC LVS DFM EMIR etc.
Basic understanding of fabrication steps and flow.
Experience in Testchip integration and analysis will be an added advantage.
Preferred Qualifications:
Good knowledge of CMOS technology
Handson knowledge of stateoftheart standard cell layout flows
Programming experience applicable to design flow automation tasks
The ability to work within a very dynamic interdisciplinary environment as well as dedicated knowledge of 45/32/28nm and below technology nodes are an advantage.
You are flexible highly motivated and have a teamoriented working style.
You have shown the ability to communicate as well as work efficiently in an international multidisciplinary environment.
Strong written and verbal communication skills in English are a must.
GlobalFoundries is an equal opportunity employer cultivating a diverse and inclusive workforce. We believe having a multicultural workplace enhances productivity efficiency and innovation whilst our employees feel truly respected valued and heard.
As an affirmative employer all qualified applicants are considered for employment regardless of age ethnicity marital status citizenship race religion political affiliation gender sexual orientation and medical and/or physical abilities.
All offers of employment with GlobalFoundries are conditioned upon the successful completion of background checks medical screenings as applicable and subject to the respective local laws and regulations.
Information about our benefits you can find here: https://gf/aboutus/careers/opportunitiesasia
Employment Type
Full-Time
