DSP or Serdes RTL Lead Digital Design Engineer
DSP or Serdes RTL Lead Digital Design Engineer
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$ 114800 - 213200
1 Vacancy
Job Description
At Cadence we hire and develop leaders and innovators who want to make an impact on the world of technology.
This is an opportunity to join a dynamic and growing team of engineers developing highspeed PMA layer IP for industrystandard protocols. The successful candidate will be a highly selfmotivated and resultsoriented member of a small team of engineers that can learn and improve existing digital flows.The candidate will primarily be responsible for frontend coding scripting and developing flows at all phases of the digital design and functional verification.It is further expected that the candidate will be able to work as part of a small and focused team of engineers and will be able to collaborate successfully as needed with the digital analog and application teams.Candidate should be willing to work full time in the San Jose office. A Cadence satellite office (if senior with extensive SerDes exp. will be considered.
Position Requirements
This team is focused on DSP and/or High Speed Serdes. The ideal candidate will have at least 3 plus years of actual work experience in SerDes as well as a thorough understanding of the endtoend digital design flow in order to accurately and efficiently collaborate with all members of the technical staff both analog and digital regarding overall project development progress and status.This includes but is not limited to:
- Digital microarchitecture definition and documentation
- RTL logic design debug and functional verification
- Strong background in DSP and algorithms is a plus.
- Familiar with the PMA/PMD/PCS layers of the Ethernet protocol is a plus.
- Understanding of digital architecture tradeoffs for power performance and area
- Understanding of proper handling of multiple asynchronous clock domains and their crossings
- Understanding of Lint checks and proper resolution of errors
- Understanding synthesis timing constraints static timing analysis and constraint development
- Understanding of fundamental physical design flows and stages
- Understanding impacts of analog and mixedsignal design and verification on digitalontop development flow.
- Exhibit excellent communication skills and be selfmotivated and well organized.
- Experience with FPGA and/or emulation platform is a plus.
- Firmware development of embedded microcontroller systems is a plus.
Substantial experience with Verilog is required as are excellent logic and debug skills. Engineering expertise in mixedsignal IP development procedures and Ethernet connectivity protocol knowledge are also strongly preferred.
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The annual salary range for California is $114800 to $213200. You may also be eligible to receive incentive compensation: bonus equity and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications skill level competencies and work location. Our benefits programs include: paid vacation and paid holidays 401(k) plan with employer match employee stock purchase plan a variety of medical dental and vision plan options and more.
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Employment Type
Full-Time
