IC Layout Design Engineer Onsite (hybrid) or fullyremote Fulltime/employee OT pay Benefits Bonus US Citizen or US Permanent Resident (preferred) TN or H1B visa ok
Requirements: 3 years of experience in layout and verification tools and methodologies for RF/Analog/MixedSignal ICs 3 years of experience in Cadence layout (Virtuoso VXL) and Calibre verification (ERC DRC LVS) FinFET experience is a plus Debugging and analytical skills with complex technical concepts Experience in DFM hierarchical layout construction for efficient verification and integration Must understand techniques for managing layout dependent effects i.e. IR drop RC delay electronmigration self heating and crosstalk Comprehensive understanding of matching shielding guard rings and latch up Proficiency in PERL or SKILL scripting is a plus Strong verbal and written communication BSEE is a plus or AA degree in IC Layout
Responsibilities: Delivering on project assignments with integrity commitment and excellence Efficiently laying out sensitive RF Analog and Mixed Signal circuits conforming to all physical design verification (PDV) requirements while balancing demanding area performance and power specifications Identifying quality and reliability improvements in IC circuit and layout design Supporting or performing design verification from subblock up through toplevel Collaborating effectively with local and remote team members Developing accurate layout design schedules and resource estimates Proactively looking for continuous improvement opportunities in the flow layout and design methodologies
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