Working with a design team to develop advanced DRAM and Emerging memory products using stateoftheart memory technologies.
Verifying highdensity memory chips (up to 32Gb) with huge scale of circuit capability (over 4M transistors) ultrahighspeed designs and complex functionality.
Evaluating block level functionality/fullchip level and providing solutions for functionally correct design.
Collaborating with various design and verification teams across the globe.
Providing verification support to design projects by simulating analyzing and debugging presilicon block level/full chip designs.
Developing and maintaining test benches and test vectors using simulation tools and running regressions for coverage analysis and improvements.
Participating in the development of new verification flows for challenges in DRAM and emerging memory design.
Developing verification methodology and verification environments for advanced DRAM and emerging memory products.
Understanding and using digital/mixed signal circuits and verification tools like Virtuoso Xcellium Simvision vsim Waveview Finseim Hspice.
Writing Verilog and Real Number Models.
Building SV testbenches at Block and Fullchip Level.
Using SV UVM based Verification and scripting using Perl and Python.
Previous work experience in DRAM memory related fields is preferred.
Good communication debugging skills and ability to work well in a team are required.
Understanding the usage of tools like Cadence (Xcellium Simvision) Synopsys (VCS Verdi) and Mentor (Questasim) simulators.