ASIC STA Engineer NRIs Return to INDIA

Skills Required :

• • 1020 years of proven experience in Synthesis/STA
  • Good understanding of overall design Flow RTL to GDS.
  • Experience in signing off the full chip synthesis/STA for tapeouts
  • Handson Experience in constraint generation and management for hierarchical designs.
  • Detailed Understanding of DFT Constraints.
  • Handon Synthesis & STA Experience on Lower Node Technologies with Synopsys/Cadence Tools.
  • Handson Experience on Equivalent Checks with Synopsys / Cadence Tools.
  • Good knowledge of Timing Budgets.
  • Knowledge of Perl / TCL / Python scripting language
  • Experience in multivoltage designs using CPF/UPF.
  • Good understanding of the Chip Interface Constraint Generation & Timing Closure.
  • Handson experience in power analysis using PTPX
  • Good understanding of VHDL / Verilog Constructs.

Responsibilities:

• • Responsible for Block/ Chip Tile Synthesis to achieve the best PPA.
  • Constraint Generation & Maintenance for Block / SOC for sophisticated hierarchical Designs for all the Modes.
  • Interaction with Design DFT IP&PD teams for Timing Convergence & Resolving Constraint Conflicts.
  • Able to work on lowpower & verify lowpower intent with minimal direction.
  • Responsible for Logical equivalence checks & Low Power Checks.
  • Early RTL analysis for Clocking Power DFT coverage & suggestions to the Designer on the improvements.
  • Support Verification team to enable GLS.