Circuit Design Engineer

Note: US Citizen required for this position
Schedule 4/10A1st Shift

Job Description:
Circuit Design Engineer needed to develop CCA requirements CCA design CCA analysis CCA layout support complete component procurement & kitting.
PCB/CCA procurement checkout & integration support.
Comply with CCA Design Assurance process requirements.
Document CCA checkout procedures and development logs.
Support Packaging engineer with CCA footprint and interface cable design.
CCAs include highspeed serial and sensitive analog signals including stateoftheart FPGAs RFSoCs ADCs PCIe Ethernet SRIO etc.
High driven individual willing to work with a SR engineer to learn and take over responsibility.
Candidate will also perform sustainment of design of a standalone functional test setup planning and execution of Environmental Design Verification Testing (DVT) EMI DVT EIB and Power Transfer support to integration with the other test equipment or hardware including Telemetry Interface support to testing at remote location or lab and support integration and functionality in the Hardware in the Loop (HWIL) lab for an upcoming flight test.
The candidate must have strong analog design background to help integrate and troubleshoot hardware issue in lab environment.
There are two position where there are overlap responsibility in both Circuit Design and supporting existing HWIL test setup.
Candidate able perform circuit design hardware integration and troubleshooting analog electronics / PCBs.

Required skillset:
24 years experience in develop and analysis digital and analog circuit.
24 years Handon experience with circuit card and electronics hardware.
6 plus years experience with Hardware integration experience specially on electronics.
24 years experience with circuit analysis tool like SPICE.
24 years experience Document circuit checkout procedure and test verification.

Desire Skillset:
Familiar with Siemen Xpedition circuit design tools
Familiar with circuit design include highspeed serial and sensitive analog signals including stateoftheart FPGAs RFSoCs ADCs PCIe Ethernet SRIO etc.
Familiar with Hardware in a Loop (HWIL) setup to support system level verification
Familiar with peer review process
Familiar with electronics interfaces like cabling between subsystem
RF background is a plus.


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