Posted on :
04-03-2024
Employer Active
1 Vacancy
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Job Description
Req ID : 2590197
Position Name : STA
Experience Required : 6 9 years
Location : Pan India
Notice Period : Immediate 15 days
JDS :
Desirable to have exposure in full chip implementation
Tool Experience: Design Complier Fusion Complier/ICCII ICV Conformal LEC StarRCXT Primetime Candence Innovus
48 years experience in Static Timing Analysis & Timing closure
Strong Fundamental in STA and Tools like Primetime (SNPS)/ Cadence Tools
Work closely with crossfunctional and PD teams to review full chip sub system and partitions level Static Timing Analysis (STA)
Strong Understanding of Device physics to take call on DRC and Fixing Timing ECO.
Must have Constraints Understanding & should be well capable to understanding design Sanity.
Must have been exposed to full flow of Timing Signoff.
Scripting knowledge of TCL/PERL.
design,primetime,static timing analysis,eco
Employment Type
Full Time
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