Memory Layout Engine....
Memory Layout Engineer
Posted on :
06-02-2024
Employer Active
1 Vacancy
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Monthly Salary
Not Disclosed
Salary Not Disclosed
Vacancy
1 Vacancy
Posted on :
06-02-2024
Job Description
Req ID : 2511968
Responsible for Memory Compiler layout development and verification.
Responsible for Layout design and development of Memory blocks such as Array Row/ Column decoder sense amplifier precharge Control blocks for SRAM.
Perform layout verification like LVS/ DRC/ Latchup quality check and documentation.
Responsible for ontime delivery of blocklevel layouts with acceptable quality.
lvs,layout design and development of memory blocks,drc,quality check,lvs/ drc/ latchup verification,memory layout,lacthup,memory compiler layout development,documentation
Employment Type
Full Time
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