Principal Engineer DFT

Our client is a leading provider of embedded control applications. Their product portfolio comprises general purpose and specialized 8-bit, 16-bit, and 32-bit microcontrollers, 32-bit microprocessors, field-programmable gate array (FPGA) products, a broad spectrum of high-performance linear, mixed-signal, power management, thermal management, radio frequency (RF), timing, safety, security, wired connectivity and wireless connectivity devices, as well as serial Electrically Erasable Programmable Read Only Memory (EEPROM), Serial Flash memories, Parallel Flash memories, and serial Static Random Access Memory (SRAM). They also license Flash-IP solutions that are incorporated in a broad range of products.

The AES Design team in Bangalore is looking for an experienced and motivated Design-For-Test Technical Staff Engineer to provide test hardware solution for various microchip Business units. As a member of test development team,you will be responsible for understanding the existing DFT test structures and clock strategy used across multiple business units and provide architectural improvements to improve test coverage. The candidate should have experience with ATPG and MBIST. The candidate should have in depth knowledge of Tessent/Modus tool execution.

Requirements

Job Requirements

Qualified applicants will possess the following skills / experience:

Hands on expertise on handling DFT on hierarchical designs.

Hands on expertise on Tessent/Modus ATPG tool for DFT setup and pattern generations.

Hands on expertise on Tessent/Modus MBIST tool for MBIST hardware generation.

Hands on expertise on Tessent/Modus diagnosis tool for on-silicon debug.

Hands on expertise SCAN pattern simulations and debug.

ATPG with the pattern delivery to the test engineering team.

Sound knowledge of Scan Stitching, Scan Compression, MBIST & JTAG Techniques.

Should have good post silicon DFT bring-up and debug experience.

Should have a good knowledge in simulation debug and prior experience at SoC level.

Excellent written and verbal communication skills.

Self-motivated team player with strong problem-solving skills to collaborate with various teams to achieve desired goals.

Experience:

BE/BThech or ME/MTech in Electronics or related field with 10+ years of experience

Job Requirements Qualified applicants will possess the following skills / experience: Hands on expertise on handling DFT on hierarchical designs. Hands on expertise on Tessent/Modus ATPG tool for DFT setup and pattern generations. Hands on expertise on Tessent/Modus MBIST tool for MBIST hardware generation. Hands on expertise on Tessent/Modus diagnosis tool for on-silicon debug. Hands on expertise SCAN pattern simulations and debug. ATPG with the pattern delivery to the test engineering team. Sound knowledge of Scan Stitching, Scan Compression, MBIST & JTAG Techniques. Should have good post silicon DFT bring-up and debug experience. Should have a good knowledge in simulation debug and prior experience at SoC level. Excellent written and verbal communication skills. Self-motivated team player with strong problem-solving skills to collaborate with various teams to achieve desired goals. Experience: BE/BThech or ME/MTech in Electronics or related field with 10+ years of experience