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Sr. Principal Engineer - Post-Silicon Validation
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Sr. Principal Engine....
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Sr. Principal Engineer - Post-Silicon Validation

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Job Location

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Bengaluru - India

Monthly Salary

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Not Disclosed

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Salary Not Disclosed

Vacancy

1 Vacancy

Job Description

Req ID : 1736894
About Arm
Arm is at the heart of the world's most advanced digital products. Our technology enables the creation of new markets and transformation of industries and society. We design scalable, energy efficient-processors and related technologies to deliver the intelligence in applications ranging from sensors to servers, including smartphones, tablets, enterprise infrastructure and the Internet of Things.
Our innovative technology is licensed by Arm Partners who have shipped more than 200 billion Systems on Chip (SoCs) containing our intellectual property since the company began in 1990. Together with our Connected Community, we are breaking down barriers to innovation for developers, designers and engineers, ensuring a fast, reliable route to market for leading electronics companies.
With 125 Arm-powered products shipped every second, we'll be in over a trillion smart devices by 2035. Your smartphone, award-winning VR gaming, the world's fastest supercomputer our engineers are designing the advanced core processors leading the race towards a connected, autonomous, hyper-performance future.Job Overview
Sr. Principal Engineer for Post-Silicon validation for Test Chip program and related future roadmap. Responsible for owning Post-Si validation workstreams ex: ATE, Board level validations, drive infrastructure development, capabilities, methodology, and debug of issues in post-Silicon validation. Influence internal and external teams to improve product quality and TTM.Responsibilities:
Responsible for Post-Silicon PoC/roadmap delivery.
Develop methodologies for PVT (Process, Voltage, and Temperature), SLT (System Level Test), SVC (Voltage corners across Process), and general validation coverage for the SOCs.
Drives capabilities and improvements to the system validation platform to improve test coverage, debug capability and board level functionality. This includes integrating debug tools, power measurements, voltage control, logging, and other board level architecture to improve validation quality, debug times, coverage, and automation.
Owns System Validation SW infrastructure, test methodology, and debug techniques across the validation team. Drive/review test plans and results to ensure resources are working in areas with the largest return on investment.
Develops methodology to debug and root-cause PVT marginality issues using the LADA to improve product VMins and maximum frequency targets. Follow through from pre-silicon design tools timing closure to post-silicon validation results by motivating changes into design timing tools to more accurately simulate real-world silicon behavior.
Intimately involved in all debug activities from pre-silicon to customer ramp. This includes driving silicon fixes into future products and revisions, finding and implementing SW and HW solutions to work-around silicon and system bugs, and influencing product engineering (manufacturing) test programs, kill limits, voltage guard-bands and test SW to improve yields and DPM.
As the last line of defense on customer level issues. Directly interacts with customer teams, SW teams, design teams, application Engineers to quickly root-cause and resolve customer lines-down and ramp limiting issues. Ultimate goal is to ramp products quickly and improve TTM. Continuously drive validation improvements to find bugs earlier in the product
Builds close relationships with external teams to improve quality, and develop new cross-group BKMs to improve product quality and TTM.
Owns thermal management scheme for the company used to ensure silicon operates within thermal limits and maintains basic level of performance. Drive characterization of silicon across process, temperature, and voltage for all major sub-systems in the SOC. Apply characterization to thermal system model to improve performance and minimize power as the device approaches the thermal limits. Deliver SW frequency and voltage limits per block per product to ensure silicon operates within specification and meets minimal performance targets. Work closely with SW teams across the world to test and validate the Thermal Management Scheme ensuring it meets customer requirements. Drive kill limits to Product Engineering to ensure product quality and maintain high product yields
Continuously, develops new capabilities to improve validation efficiency, coverage and debug, then train junior engineering take over ownership going forward.
Product Definition: Play a key role in product definition, design architecture, SW development, and within product engineering teams to improve product features and TTM. Influence design to reduce total engineering resources, rather than just design resources. Influence change across product groups that have impacts to product quality and features and remove changes that dont chip in.
Providing technical guidance, coaching, and mentoring of highly skilled senior and junior engineer and possible line management responsibilities of a small team.
Working with your teams and project managers to plan, schedule and deliver roadmap.
Team development, plan and use the assigned engineers creatively to deliver on the engineering commitments successfully
Essential Experience:
20+ yrs of experience with strong technical (pre as well post-Si validation)
Experience in driving and coordinating projects under ambiguous circumstances and achieve the best result within defined timeline.
Deep understanding of SoC architecture across one or more market segments
Hands on experience of post-Si validation activities, tool, debugs etc
Consistent track record of execution and/or methodology development and deployment on complex projects, individually or in a team
Great influencing and presentation skills!
Excellent interpersonal and communication skills!
Experience is cross geo team interactions.
Growth mindset and looking for continuous improvement.
Desirable Experience:
Awareness of CPU/System architecture features (such as caches, MMU, SMP, coherency, pipelines)
Exposure to various market segments like Client, Infrastructure, Embedded, IoT
General understanding of Arm-based Systems and protocols like AMBA AXI and/or CHI#LI-KR2

Employment Type

Full Time

Company Industry

IT - Software Services

About Company

10 employees
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