Technical Staff Engineer – Verification

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Job Description:

The dsPIC Business Unit is seeking a Technical Staff Engineer Verification to join verification team in Bangalore India. The successful candidate will

be responsible for doing IP level pre-silicon verification. The role involves collaboration with team members in USA India and other global

corporate teams.

Job Responsibilities:

Develop and maintain UVM/System Verilog based verification environments and Formal Tool based verification environments.

Define test plans implement constrained-random and directed tests develop assertions coverage and drive coverage

closure.

Debug RTL and testbench issues perform root cause analysis and collaborate with design and architecture teams to resolve bugs.

Analyze code and functional coverage metrics to ensure comprehensive verification closure.

Work with product development team to integrate the UVM test bench and tests at the SoC level.

Collaborate with Architect Design and applications groups to verify the products and IP requirements.

Continuously improve verification methodology reuse and efficiency.

Requirements/Qualifications:

Bachelors or masters degree in electrical/Electronics/Computer Engineering or related field.

Minimum 8 years of experience in ASIC/SoC functional verification.

Hand on experience in System Verilog language assertions and UVM methodology.

Hands-on experience in developing IP level SoC-level verification environments with UVM methodology.

Good understanding of Digital Design RTL fundamentals and simulation/debug flows.

Strong analytical and debugging skills.

Excellent communication teamwork and problem-solving abilities.

Highly motivated detail-oriented and committed to delivering quality results.

Travel Time:

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