Staff Engineer, STA

Senior/Staff STA (Static Timing Analysis) Engineer 

The STA Engineer is responsible for ensuring robust timing closure and signoff readiness for block- and full-chip designs across all modes and corners. This role owns timing constraint development and validation performs detailed setup/hold and variation-aware analysis and partners closely with Synthesis CTS Physical Design and Design teams to debug violations and drive ECO-based optimizations through tapeout. 

What youll do 

• Perform full-chip and block-level Static Timing Analysis (STA) across all modes and corners. 
• Analyze and debug setup hold recovery removal clock gating and signal integrity-related timing violations. 
• Work closely with Physical Design Synthesis CTS and Design teams to achieve timing closure. 
• Develop and maintain timing constraints including SDC creation validation and signoff readiness. 
• Drive timing closure through ECO implementation and timing optimization. 
• Analyze timing impact due to process voltage and temperature variations. 
• Support timing signoff for pre-layout and post-layout stages. 
• Perform cross-functional reviews for timing convergence and provide recommendations. 
• Generate timing reports and communicate closure status to project stakeholders. 

Qualifications :

What were looking for 

• 412 years of experience in Static Timing Analysis (STA) and timing closure for block and/or full-chip designs. 
• Strong understanding of CMOS fundamentals timing concepts and semiconductor design flow. 
• Hands-on experience in setup/hold analysis path-based analysis OCV/AOCV/POCV derates and MMMC concepts. 
• Good understanding of clock tree clock uncertainty latency skew and jitter. 
• Experience in timing constraints development and debugging. 
• Strong knowledge of SDC timing exceptions false paths multicycle paths and case analysis. 
• Familiarity with timing closure techniques and ECO methodologies. 
• Hands-on experience with industry-standard STA tools such as Synopsys PrimeTime or Cadence Tempus. 
• Good scripting skills in Tcl Perl or Python. 
• Ability to analyze and resolve timing violations independently. 

Nice to have 

• Exposure to low-power timing analysis and UPF/CPF-aware STA. 
• Familiarity with SI-aware timing Crosstalk analysis and IR-drop-aware timing closure. 
• Knowledge of advanced technology nodes and variation-aware signoff methodologies. 
• Exposure to automation and flow development. 
• Experience in cross-functional collaboration with PD RTL and Signoff teams. 

Additional Information :

Renesas is an embedded semiconductor solution provider driven by its Purpose To Make Our Lives Easier. With a global team of over 21000 engineers and problem solvers in more than 30 countries we offer the opportunity to work on worldleading technology for Automotive Industrial Infrastructure and IoT shaping a safer healthier greener and smarter future.

At Renesas TAGIE is our culture grounded in being Transparent Agile Global Innovative and Entrepreneurial. It shapes how we work grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.

We believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.

Are you ready to join our team and shape the future with us

Renesas Electronics is an equal opportunity and affirmative action employer committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex race religion national origin gender gender identity gender expression age sexual orientation military status veteran status or any other basis protected by law. For more information please read our Diversity & Inclusion Statement.

Remote Work :

No

Employment Type :

Full-time