Staff Digital Design Engineer

Role Summary

We are seeking a Senior Lead Digital Designer to lead the architecture implementation and integration of digital subsystems for Automotive Ethernet PHY products (10BASET1S 100BASET1 1000BASET1 and multigig automotive SerDes technologies).

The role involves driving digital micro-architecture state machines PCS functionality safety mechanisms and endtoend digital design across the PHY.

Key Responsibilities

1. Architecture & Technical Leadership

• Define and own digital subsystem microarchitecture for Automotive Ethernet PHYs including:

  • PCS pipelines and encoding/decoding logic

  • Scramblers/descramblers CRC engines alignment & framing

  • Packet processing link monitoring error handling

  • Interface logic (MII RMII RGMII GMII XGMII depending on product line)

  • Processor based SoC design

• Perform systemlevel partitioning between digital analog/mixed-signal and firmware components.

• Lead feasibility studies power/performance trade-offs and digital architecture exploration.

2. RTL Design & Implementation

• Develop high-quality RTL (Verilog/SystemVerilog) for control datapath and protocol logic.

• Drive digital front-end flows including:

  • Lint CDC/RDC reset architecture synthesis guidance

  • Timing constraints and logic optimization

• Work with DV to define coverage goals corner cases and feature verification plans.

3. SystemLevel Ownership

• Translate system requirements IEEE 802.3 specifications and architecture documents into robust digital designs.

• Work with mixed-signal teams to define:

  • Control interfaces to analog frontend blocks

  • Calibration engines register programming flows and digitalanalog interaction models

• Contribute to bringup sequences compliance testing and system validation.

4. Automotive Quality & Functional Safety

• Ensure compliance with Automotive Ethernet standards ISO 26262 and AECQ100 expectations.

• Define and implement:

  • Safety mechanisms (BIST LBIST/MBIST error detection schemes)

  • Diagnostic monitors timeout recovery logic watchdogs and fault reporting

• Participate in FMEDA DFA and functional safety analysis.

Required Qualifications

• Masters in Electrical Engineering Computer Engineering or related discipline.

• 7 years experience in digital design for PHY SerDes networking ASICs or communication ICs.

• Strong expertise in:

  • Verilog/SystemVerilog RTL design

  • Highspeed digital logic state machines control logic

  • IEEE 802.3 Ethernet PCS link training and system control flows

  • Synthesis STA CDC/RDC methodology

• Proven track record across multiple production tape-outs.

Preferred Qualifications

• Experience with Automotive Ethernet standards: 10BASET1S 100BASET1 1000BASET1 10GBASET1.

• Familiarity with PHY firmware-driven initialization and configuration flows.

• Strong debugging skills with logic analyzers protocol analyzers and post-silicon validation.

• Background in safetycritical digital logic designs.