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STA & Full Chip Design Engineer
Job Location:
Monthly Salary:
Not provided by the employer
Monthly Salary:
Experience Required:
3-5years
Experience Required:
Posted:
24 May 2026 (30+ days ago)
Posted:
Application Deadline:
21 August 2026
Application Deadline:
Vacancies:
1 Vacancy
Vacancies:
Job Summary
Hiring: STA & Full Chip Design Engineer
Location: Bangalore
Experience: 3 5 Years
Budget: 3040% hike on current CTC
Notice Period: Immediate joiners (Join before 30th April)
Role Overview
We are looking for STA & Full Chip Design Engineers with strong expertise in timing analysis closure and sign-off. Ideal candidates should be ready to contribute from day one in a fast-paced semiconductor environment.
Key Responsibilities
- Perform Static Timing Analysis (STA) across corners/modes
- Drive timing closure and optimization
- Handle full chip timing sign-off activities
- Analyze and fix setup/hold violations
- Collaborate with PD RTL and verification teams
Key Requirements
- 35 years of core STA/Full Chip Design experience
- Strong expertise in timing closure & sign-off
- Experience in multi-corner multi-mode (MCMM) analysis
- Good understanding of ASIC design flow
Why Join
- Work on advanced chip design projects
- High-impact role with growth opportunities
- Competitive compensation
Required Skills:
Key Responsibilities Perform Static Timing Analysis (STA) across corners/modes Drive timing closure and optimization Handle full chip timing sign-off activities Analyze and fix setup/hold violations Collaborate with PD RTL and verification teams
Required Education:
Bachelors or Masters degree in Computer Science Information Technology Software Engineering or a related field
