Sr Staff Staff Engineer, RTL Design

• Collaborate with system architects and micro-architects to define high-level implementable SoC specifications.
• Own end-to-end SOC RTL delivery while analysing and optimizing design for power performance and area (PPA) targets. Influence SoC definition features and adopt physical design friendly partitioning.
• Lead RTL design and integration of multi-subsystem SoCs supporting complex architectures with multi-core multi-power and multi-reset domains.
• Demonstrate strong proficiency with front-end flows including Lint CDC low-power (UPF) checks synthesis DFT and Static Timing Analysis (STA).
• Drive the development of robust Safety Security and Debug architectures for advanced SoCs with multiple interconnects.
• Design and integrate standard interface protocols such as AHB AXI CHI and memory interfaces including ROM RAM Flash LPDDR/DDR3/4.
• Engage cross-functionally with DFT physical design verification emulation and validation teams to ensure first-time-right silicon and on-time project delivery.
• Support post-silicon debug bring-up and validation working closely with lab and silicon validation teams.
• Continuously evaluate and adopt new design methodologies and best practices to improve productivity and shift-left the design cycle.
• Mentor junior engineers review their work and provide technical leadership and guidance across multiple design projects. Provide overall leadership and tracking of the teams goals.
• Contribute to the innovation quotient of the team via Desing Patents Industry Standard Publications AI-enabled design methodologies etc.

Qualifications :

• MTech/BTech in EE/CS with hardware engineering experience of 10 years.
• Experience in micro-architecture development RTL design front-end flows (Lint CDC low-power checks etc.) synthesis/DFT/FV/STA
• Experience with high-speed interface design and hands on knowledge of Industry standard High speed protocols like PCIe4/PCIe6/UCIe etc. is desirable.
• Experience in development of SERDES PCS/PMA logic including scrambling/descrambling data encoding/decoding block synchronization etc.
• Understanding of electrical characteristics and signoff needed for meeting PCIe/UCIe standards compliance.
• Experience with post-silicon bring-up and debug is a plus.
• Able to work with teams across the globe and possess good communication skills

Additional Information :

Renesas is an embedded semiconductor solution provider driven by its Purpose To Make Our Lives Easier. With a global team of over 21000 engineers and problem solvers in more than 30 countries we offer the opportunity to work on worldleading technology for Automotive Industrial Infrastructure and IoT shaping a safer healthier greener and smarter future.

At Renesas TAGIE is our culture grounded in being Transparent Agile Global Innovative and Entrepreneurial. It shapes how we work grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.

We believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.

Are you ready to join our team and shape the future with us

Renesas Electronics is an equal opportunity and affirmative action employer committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex race religion national origin gender gender identity gender expression age sexual orientation military status veteran status or any other basis protected by law. For more information please read our Diversity & Inclusion Statement.

Remote Work :

No

Employment Type :

Full-time