Senior Physical Design Engineer

Job Summary

NXP Semiconductors is seeking a Physical Design Engineer (G2) with strong fundamentals in digital implementation to join our growing VLSI this role you will contribute to the implementation and signoff of complex SoC/IP blocks in advanced technology nodes ensuring high-quality delivery aligned with NXPs stringent PPA (Power Performance Area) and reliability standards.

Key Responsibilities

• Execute block-level physical design from synthesized netlist to GDSII:
  • Floorplanning and power grid design
  • Placement and optimization
  • Clock Tree Synthesis (CTS)
  • Routing and post-route optimization
• Drive timing convergence across MCMM scenarios in collaboration with STA teams
• Ensure design closure including:
  • Setup/hold timing closure
  • DRC/LVS clean signoff
  • IR drop and electromigration (EM) compliance
• Debug and resolve:
  • Congestion issues
  • SI/crosstalk problems
  • Functional and physical ECOs
• Collaborate cross-functionally with:
  • RTL/design teams to improve QoR
  • DFT teams for test readiness
  • Packaging and full-chip integration teams
• Contribute to methodology improvements and automation through scripting
• Follow and enforce NXP design methodologies quality and reliability standards

Required Qualifications

• Bachelors/Masters degree in Electronics / Electrical Engineering / Microelectronics
• 35 years of experience in ASIC Physical Design
• Strong understanding of:
  • Physical design flow (FP P&R Signoff)
  • Static Timing Analysis fundamentals
  • CMOS digital design basics
• Hands-on experience with industry EDA tools:
  • Cadence (Innovus/Genus) or Synopsys (ICC2/Fusion Compiler PrimeTime)
• Good scripting skills in Tcl Python or Shell

Preferred Qualifications

• Experience in advanced nodes (16nm and below)
• Knowledge of:
  • Low-power design flows (UPF/CPF)
  • Multi-voltage / multi-domain designs
  • High-speed interfaces (PCIe DDR Automotive SerDes)
• Familiarity with physical verification tools (Calibre Pegasus)