Senior AMS Design Verification Engineer AMS DV Lead

• Location: Bengaluru Hyderabad India
• Work Mode: Onsite / Hybrid
• Experience: 5 10 Years

We are seeking an experienced AMS Design Verification Engineer / Lead to drive verification of complex mixed-signal IPs and SoCs. The role involves developing AMS verification methodologies building reusable verification environments creating behavioral models and supporting full-chip mixed-signal integration. Candidates should possess strong expertise in SystemVerilog/UVM-based AMS verification and mixed-signal simulation flows.

• Develop and maintain AMS verification environments for mixed-signal IP and SoC designs.
• Build reusable SystemVerilog/UVM-based AMS testbenches from scratch.
• Define and execute AMS verification strategies and verification plans.
• Develop behavioral models using SV-RNM Verilog-AMS wreal and electrical disciplines.
• Collaborate with analog digital and design teams to ensure verification completeness.
• Perform block-level and SoC-level mixed-signal verification.
• Execute regression runs and analyze verification results.
• Debug failures using waveform analysis simulation logs and schematic correlation.
• Validate model accuracy against analog circuit behavior.
• Support top-level integration and mixed-signal subsystem verification.
• Drive coverage closure and verification signoff activities.
• Mentor junior engineers and contribute to AMS verification methodology improvements (Lead role).

• Bachelors or Masters degree in Electronics Electrical Engineering Microelectronics VLSI or related field.
• 5 10 years of experience in AMS Design Verification.
• Strong understanding of mixed-signal verification methodologies.
• Experience in verifying analog and mixed-signal IPs within complex SoCs.
• Proven experience in AMS behavioral modeling and verification environment development.

• AMS Verification Methodology
• Mixed-Signal Verification
• SoC AMS Verification
• Verification Planning
• Coverage-Driven Verification

• SystemVerilog
• UVM
• SV-RNM (SystemVerilog Real Number Modeling)
• Verilog-AMS
• wreal Modeling

• Real Number Models (RNM)
• Analog Behavioral Models
• Electrical Discipline Modeling
• Mixed-Signal Abstraction Techniques

• Cadence Virtuoso
• Cadence ADE Assembler
• Cadence Xcelium
• Cadence VIVA
• Cadence SimVision

• Waveform Debug
• Simulation Debug
• Schematic-Level Correlation
• Model Validation
• Regression Analysis

• Analog Circuit Fundamentals
• Digital Design Flow
• Mixed-Signal SoC Integration
• Top-Level Verification