Principal Engineer- Custom Layout (High-Speed Interface IP)

Job Summary:

We are seeking an experienced Principal Custom Layout Engineer to lead the physical implementation of advanced high-speed analog and mixed-signal circuits for next-generation interface IPs. The successful candidate will be responsible for the layout design floorplanning optimization and signoff of critical analog and mixed-signal blocks including DFE CTLE PLLs CDRs Transmitters Receivers DLLs and SerDes subsystems. 

The ideal candidate will have 15 years of custom layout experience after completing a Masters or Bachelors degree from a reputed university with a proven record of delivering silicon-proven designs in advanced process nodes such as 5nm and 3nm. The candidate should be able to independently drive complex projects and mentor a team of 34 junior layout engineers. 

Key Responsibilities:

• Lead the custom layout development of high-performance analog and mixed-signal IPs for advanced semiconductor products. 
• Independently drive complex custom layout projects from floorplanning through tapeout. 
• Own physical implementation for critical building blocks such as rCTLE DFE PLL etc. 
• Define floorplanning strategies to achieve aggressive performance area power and yield targets. 
• Perform transistor-level and device matching-aware layouts using industry best practices. 
• Drive physical verification and signoff activities including DRC LVS ERC PERC density verification and EMIR analysis. 
• Work closely with Analog Design Digital Design SI Packaging and Product Engineering teams to ensure successful product execution. 
• Support silicon bring-up debug characterization and production qualification activities. 
• Develop and institutionalize layout methodologies and best practices across the organization. 

Qualifications :

• Electrical Engineering Electronics Engineering VLSI Design or related discipline from a reputed university. 
• 15 years of industry experience in custom layout design. 
• Extensive experience in custom layout of analog and mixed-signal circuits in advanced CMOS technologies. 
• Strong understanding of:  

1. Analog layout fundamentals 
2. Device matching techniques 
3. High-speed signal routing 
4. Noise coupling mechanisms 
5. Parasitic extraction and optimization 
6. Manufacturing process variations 

• Demonstrated track record of delivering successful silicon in advanced technology nodes. 

Additional Information :

Renesas is an embedded semiconductor solution provider driven by its Purpose To Make Our Lives Easier. With a global team of over 21000 engineers and problem solvers in more than 30 countries we offer the opportunity to work on worldleading technology for Automotive Industrial Infrastructure and IoT shaping a safer healthier greener and smarter future.

At Renesas TAGIE is our culture grounded in being Transparent Agile Global Innovative and Entrepreneurial. It shapes how we work grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.

We believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.

Are you ready to join our team and shape the future with us

Renesas Electronics is an equal opportunity and affirmative action employer committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex race religion national origin gender gender identity gender expression age sexual orientation military status veteran status or any other basis protected by law. For more information please read our Diversity & Inclusion Statement.

Remote Work :

No

Employment Type :

Full-time