Principal Analog Design Engineer

We are seeking an experienced Analog Design Engineer with 12-18 years of expertise in high-performance PLL and clocking solutions to join our product development team. The candidate will lead the design and development of advanced clock generation distribution synchronization and timing circuits for next-generation SoCs and mixed-signal products driving innovations from architecture definition through silicon validation and production.

• 12 years of experience in analog/mixed-signal IC design with strong expertise in PLL and clocking architectures.
• Deep transistor-level design experience of PLL building blocks including VCOs charge pumps phase/frequency detectors (PFDs) loop filters clock buffers bandgap references current references OPAMPs and LDOs.
• Strong understanding of jitter phase noise clock synchronization timing recovery EMC/ESD reliability and silicon robustness.
• Hands-on experience with analog design and verification tools such as Cadence Virtuoso ADE Spectre/SPICE and related EDA environments.
• Experience with silicon characterization validation yield improvement and ATE characterization.
• Strong knowledge of advanced CMOS/FinFET technologies and analog layout considerations.
• Proven ability to lead technical reviews debug silicon issues and mentor junior engineers.
• Experience with high-speed SerDes Ethernet PHYs or timing-intensive mixed-signal systems is an added advantage.

• Architect design and verify high-performance PLL clock generation clock distribution and synchronization circuits for advanced semiconductor products.
• Own end-to-end analog design execution including specification definition transistor-level implementation performance verification and silicon bring-up.
• Develop innovative analog circuit solutions to optimize jitter phase noise power consumption and overall system performance.
• Work closely with system digital layout validation and product engineering teams to define interfaces calibration methodologies and verification strategies.
• Drive reliability EMC/ESD compliance silicon characterization and yield improvement activities.
• Lead technical decision-making conduct design reviews and provide mentorship to junior engineers while contributing to the overall analog design methodology and roadmap.

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