Principal AMS Verification Engineer

We are looking for a Principal AMS Verification Engineer with strong expertise in SerDes IP verification and mixed-signal verification methodologies with 10 years of experience. The candidate will own end-to-end verification strategy for high-speed SerDes IPs work closely with analog and digital design teams and provide technical leadership across projects.

Key Responsibilities

• Own and drive AMS verification strategy for high-speed SerDes IPs from concept to signoff
• Architect and develop UVM/UVM-AMS based verification environments
• Verify complex mixed-signal SerDes subsystems across IP subsystem and SoC levels
• Develop integrate and validate RNM / Verilog-AMS / behavioral models
• Lead verification of:
  • link training initialization and adaptation
  • Multi-lane and multi-protocol SerDes operation
  • BIST PRBS loopback error injection and robustness scenarios
• Analyze and debug complex mixed-signal issues involving timing jitter noise and protocol behavior
• Drive functional assertion-based and coverage-driven verification
• Execute corner PVT stress and performance verification
• Collaborate closely with analog design digital RTL architecture and validation teams
• Mentor and technically guide junior verification engineers
• Contribute to silicon bring-up post-silicon debug and correlation activities (where applicable)

Required Technical Skills

AMS & Verification Methodology

• Strong hands-on experience with SystemVerilog UVM and UVM-AMS
• Expertise in Verilog-AMS / AMS RNM / wreal modeling
• Experience with mixed-signal simulators such as: Cadence Xcelium AMS Synopsys VCS AMS Siemens Questa ADMS
• Strong debugging skills in mixed-signal simulation environments

SerDes Expertise

• Deep understanding of high-speed SerDes architectures including: TX/RX data paths PLLs and CDRs Equalization (CTLE DFE FFE) Clocking jitter tolerance and signal integrity concepts
• Experience verifying SerDes protocols such as:
  • USB (Must) DisplayPort(Must)
  • PCIe Ethernet HDMI MIPI SATA (any combination)
• Experience with multi-lane multi-rate and multi-protocol SerDes IPs

Modeling & Analysis

• Ability to correlate:
  • MATLAB / Python system models(Good to have)
  • Behavioral / RNM models
  • Transistor-level simulations
• Experience balancing accuracy vs simulation performance in AMS environments

Automation & Scripting

• Proficiency in Python / Perl / Tcl
• Automation of:
  • regression flows
  • result analysis and reporting
  • coverage and verification metrics

Education

• Bachelors or Masters degree in Electrical / Electronics Engineering or related field
• Masters degree preferred for Principal-level roles

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