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Physical Design Engineer (ASICVLSI)
Job Location:
Monthly Salary:
Not provided by the employer
Monthly Salary:
Experience Required:
5-12years
Experience Required:
Posted:
24 May 2026 (30+ days ago)
Posted:
Application Deadline:
21 August 2026
Application Deadline:
Vacancies:
1 Vacancy
Vacancies:
Job Summary
Hiring: Physical Design Engineer (ASIC/VLSI)
Location: Noida
Experience: 5 12 Years
Budget: 3040% hike on current CTC
Notice Period: Immediate joiners preferred
Role Overview
We are seeking skilled Physical Design Engineers with strong expertise in end-to-end ASIC implementation and timing closure across advanced technology nodes.
Key Responsibilities
- Execute RTL-to-GDSII flow: Floorplanning Placement CTS Routing & Signoff
- Drive timing closure and optimize PPA (Power Performance Area)
- Fix setup/hold violations using STA
- Ensure DRC/LVS and IR/EM clean design
- Collaborate with RTL DFT & verification teams
Key Requirements
- 4 years in ASIC/VLSI Physical Design
- Hands-on experience with Cadence Innovus / Synopsys ICC2
- Strong expertise in STA using Synopsys PrimeTime
- Knowledge of Mentor Calibre (physical verification)
- Scripting skills in TCL/Shell/Python
Why Join
- Work on cutting-edge semiconductor designs
- High-growth performance-driven environment
- Competitive compensation
Required Skills:
4 years in ASIC/VLSI Physical Design Hands-on experience with Cadence Innovus / Synopsys ICC2 Strong expertise in STA using Synopsys PrimeTime Knowledge of Mentor Calibre (physical verification) Scripting skills in TCL/Shell/Python
Required Education:
Bachelors or Masters degree in Computer Science Information Technology Software Engineering or a related field
