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Physical Design Engineer (ASIC)
Job Location:
Monthly Salary:
Not provided by the employer
Monthly Salary:
Experience Required:
1Year
Experience Required:
Posted:
24 May 2026 (30+ days ago)
Posted:
Application Deadline:
21 August 2026
Application Deadline:
Vacancies:
1 Vacancy
Vacancies:
Job Summary
Hiring: Physical Design Engineer (ASIC)
Location: Bangalore
Experience: 1.5 4 Years
Budget: 3040% hike on current CTC
Notice Period: Immediate joiners preferred
Role Overview
We are looking for a Physical Design Engineer with hands-on experience in RTL-to-GDSII ASIC implementation across advanced nodes. You will work on high-performance chip design and contribute to full-cycle physical implementation and signoff.
Key Skills
- RTL to GDSII Flow: Floorplanning Placement CTS Routing
- Timing: STA MCMM/MMMC timing closure ECO implementation
- Tools: Synopsys ICC2 PrimeTime Design Compiler
- Signoff: DRC/LVS debugging physical verification
- Optimization: PPA (Performance Power Area) improvements
- Low Power: Power planning IR drop clock optimization
Requirements
- 1.7 years of experience in Physical Design (ASIC)
- Strong understanding of timing closure & backend flow
- Experience in advanced nodes (14nm or similar preferred)
- Good collaboration with RTL & STA teams
Why Join
- Work on cutting-edge semiconductor designs
- Exposure to advanced node technologies
- Growth-focused high-impact engineering environment
Required Skills:
Key Skills RTL to GDSII Flow: Floorplanning Placement CTS Routing Timing: STA MCMM/MMMC timing closure ECO implementation Tools: Synopsys ICC2 PrimeTime Design Compiler Signoff: DRC/LVS debugging physical verification Optimization: PPA (Performance Power Area) improvements Low Power: Power planning IR drop clock optimization
Required Education:
Bachelors or Masters degree in Computer Science Information Technology Software Engineering or a related field
