Enter a job title or keyword
Digital RTL STA Physical Design Engineer
Job Location:
Monthly Salary:
Posted:
8 October 2026 (2 days ago)
Posted:
Application Deadline:
5 January 2027
Application Deadline:
Vacancies:
1 Vacancy
Vacancies:
Job Summary
Key Responsibilities:
- RTL design and development for high-performance SoCs.
- Work on architecture microarchitecture and system-level design.
- Perform Static Timing Analysis (STA) timing closure and constraint management.
- Handle Physical Design activities including floorplanning placement CTS routing and optimization.
- Collaborate with DFT software architecture analog and backend teams.
Required Skills:
- Verilog/SystemVerilog RTL Design
- SoC Architecture & Microarchitecture
- STA SDC Timing Closure MCMM Analysis
- Physical Design (Floorplanning CTS Routing ECO)
- DFT Scan MBIST CDC
- PrimeTime or Tempus
Education: BS/MS in Electrical Engineering Computer Science or related field.
Nice to Have:
- Python/Ruby
- Regression systems and revision control tools
- Startup experience
Required Skills:
VertilogRTLSoC ArchitectureMicroarchitecture
