DFX Verification
Job Summary
We are looking for a highly motivated DFX Engineer to develop implement verify and validate advanced Design-for-Test (DFT/DFX) solutions for complex SoCs and ASICs. The candidate will work closely with Architecture Design Verification Physical Design and Post-Silicon teams to ensure robust manufacturability testability and silicon quality.
Create and execute test plans for DFX features including Scan MBIST SSN EDT IJTAG and JTAG.
Verify DFX implementations at IP subsystem and SoC levels.
Develop SystemVerilog/UVM based verification environments and test benches.
Debug regression failures and identify root causes related to design or verification.
Analyze and improve functional and code coverage.
Generate and validate Scan/ATPG patterns for production testing.
Support post-silicon bring-up debug and characterization activities.
Collaborate with cross-functional teams including Design Architecture Physical Design Validation and ATE teams.
Automate DFX flows using scripting languages and improve overall test methodologies.
Contribute to DFX architecture planning and implementation for next-generation SoCs.
Scan Insertion & Compression
ATPG Pattern Generation & Debug
MBIST / LBIST
JTAG IEEE 1500 IEEE 1687 (IJTAG)
SSN (Streaming Scan Network)
EDT (Embedded Deterministic Test)
Siemens Tessent Suite (TestKompress MBIST SSN IJTAG EDT)
Synopsys Fusion Compiler
Synopsys Design Compiler
SpyGlass
RTL and Gate-Level Simulation Tools
SystemVerilog
UVM
Assertions (SVA)
Functional and Code Coverage
SoC/IP Verification
Python
Perl
TCL
Shell Scripting
Experience in end-to-end DFX flow development.
Strong understanding of ASIC/SoC design flow from RTL to silicon.
Knowledge of STA Timing Closure LEC and Physical Design considerations.
Experience with post-silicon validation and ATE bring-up.
Exposure to high-speed interfaces such as PCIe DDR Ethernet USB CXL UCIe or SerDes is a plus.
B.E./ in Electronics Electrical Engineering VLSI Computer Engineering or related fields
Required Skills:
DFXVerification and Validation (V&V)DFTSOC