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DFT (Design for Testability) Engineer
Job Location:
Monthly Salary:
Posted:
15 August 2026 (8 hours ago)
Posted:
Application Deadline:
12 November 2026
Application Deadline:
Vacancies:
1 Vacancy
Vacancies:
Job Summary
DFT (Design for Testability) Engineer
Role Summary: We are seeking a DFT Engineer to design and implement testability structures for complex ASIC/SoC designs ensuring high test coverage manufacturing yield and silicon quality across advanced technology nodes.
Responsibilities:
Implement scan insertion ATPG pattern generation and fault coverage analysis for digital designs
Design and integrate Memory BIST (MBIST) and Logic BIST (LBIST) architectures
Develop and validate JTAG/boundary scan (IEEE 1149.1) implementations
Collaborate with RTL design teams to ensure DFT-friendly design practices are followed early in the design cycle
Analyze test coverage reports and work to close coverage gaps
Support silicon bring-up and debug using DFT structures for yield analysis
Work with EDA tools (Synopsys TestMAX/DFTMAX Cadence Modus Mentor Tessent) for ATPG and BIST implementation
Coordinate with foundry/test teams on ATE (Automated Test Equipment) pattern conversion and correlation
Required Skills: ASIC/SoC design flow Scan/ATPG MBIST/LBIST JTAG Synopsys/Cadence/Mentor DFT tools Verilog/SystemVerilog fault simulation
Experience: 58 years in DFT Engineer role with ATPG experience (Must).
Role Summary: We are seeking a DFT Engineer to design and implement testability structures for complex ASIC/SoC designs ensuring high test coverage manufacturing yield and silicon quality across advanced technology nodes.
Responsibilities:
Implement scan insertion ATPG pattern generation and fault coverage analysis for digital designs
Design and integrate Memory BIST (MBIST) and Logic BIST (LBIST) architectures
Develop and validate JTAG/boundary scan (IEEE 1149.1) implementations
Collaborate with RTL design teams to ensure DFT-friendly design practices are followed early in the design cycle
Analyze test coverage reports and work to close coverage gaps
Support silicon bring-up and debug using DFT structures for yield analysis
Work with EDA tools (Synopsys TestMAX/DFTMAX Cadence Modus Mentor Tessent) for ATPG and BIST implementation
Coordinate with foundry/test teams on ATE (Automated Test Equipment) pattern conversion and correlation
Required Skills: ASIC/SoC design flow Scan/ATPG MBIST/LBIST JTAG Synopsys/Cadence/Mentor DFT tools Verilog/SystemVerilog fault simulation
Experience: 58 years in DFT Engineer role with ATPG experience (Must).
Required Experience:
IC
