Design Verification (IP Level)

1) Design Verification (IP Level) - High-Speed Ips

a. Location :- Bangalore - Onsite client location ( WFO)

b. Total Req 6 - 1 Senior Lead 10 Years and the rest 5 to 10 Yrs experience

Extensive experience in IP-level Design Verification of High-Speed Interface IPs including PCIe USB Ethernet MIPI DDR/LPDDR SerDes CXL and UCIe. Expertise in developing scalable verification environments using SystemVerilog and UVM methodologies protocol compliance verification functional and code coverage closure assertion-based verification (SVA) and low-power verification.

Key Responsibilities:-

Develop and maintain UVM-based verification environments for High-Speed IPs.

Create verification plans test cases checkers scoreboards and coverage models.

Perform protocol compliance and interoperability verification.

Develop SystemVerilog Assertions (SVA) for protocol and functional checks.

Execute constrained-random and directed verification strategies.

Debug RTL simulation and protocol-level issues.

Drive coverage closure regression management and sign-off activities.

Collaborate with Architecture RTL Design Validation and Physical Design teams.

Required Skills:-

SystemVerilog UVM SVA

High-Speed Protocols: PCIe Gen4/Gen5/Gen6 USB3.x/USB4 Ethernet MIPI DDR/LPDDR CXL UCIe

Verification planning and coverage-driven verification

Protocol analyzers and VIP integration

Simulation tools: VCS Xcelium Questa

Debug tools and waveform analysis

Deliverables:-

Verification Plan (VPlan)

Testbench Architecture

Regression and Coverage Reports

Functional and Code Coverage Closure

Verification Sign-off Report

Compliance Certification Support

Required Skills:

Design Verification TestingUVM