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ASIC RTL Design Engineer
Job Location:
Monthly Salary:
Experience Required:
Posted:
24 May 2026 (30+ days ago)
Posted:
Application Deadline:
21 August 2026
Application Deadline:
Vacancies:
1 Vacancy
Vacancies:
Job Summary
Job Description ASIC RTL Design Engineer
Location Bangalore India
Experience 510 Years
Position Overview
We are seeking highly skilled ASIC RTL Design Engineers with strong expertise in RTL coding
micro-architecture development and SoC/ASIC design flows. The ideal candidate will be
responsible for developing high-performance and power-efficient RTL designs for next-
generation semiconductor products across networking AI/ML compute or high-speed digital
systems.
The role requires deep understanding of digital design fundamentals chip-level integration and
front-end VLSI design methodologies with strong ownership across the RTL development
lifecycle.
Key Responsibilities
Develop RTL code for complex ASIC/SoC modules using Verilog/SystemVerilog.
Participate in architecture and micro-architecture discussions for high-performance
digital designs.
Translate architectural specifications into optimized RTL implementations.
Work on block-level and chip-level RTL integration.
Optimize designs for Power Performance and Area (PPA).
Collaborate closely with Verification Physical Design DFT STA and Architecture teams.
Perform RTL debugging linting CDC checks and synthesis validation.
Support functional verification and resolve design-related issues.
Ensure adherence to coding guidelines and RTL design best practices.
Participate in design reviews and technical discussions.
Required Skills & Qualifications
Bachelors or Masters degree in Electronics Electrical Engineering VLSI or related field.
510 years of hands-on experience in ASIC RTL Design / Front-End VLSI Design.
Strong expertise in:
o Verilog / SystemVerilog
o RTL Coding
o ASIC/SoC Design
o Micro-Architecture
o Digital Design Fundamentals
Strong understanding of:
o FSM design
o Pipelining
o Clock domain crossing (CDC)
o Reset architecture
o Timing concepts
o Low-power design methodologies
Experience with synthesis linting and RTL quality checks.
Good debugging and analytical skills.
Ability to work in fast-paced semiconductor development environments.
Preferred Skills
Experience with Networking ASICs AI/ML accelerators CPU/GPU Storage or Multimedia
SoCs.
Exposure to AMBA protocols (AXI/AHB/APB).
Familiarity with scripting languages such as Perl Python or Tcl.
Exposure to FPGA prototyping flows.
Understanding of Verification methodologies and simulation environments.
Experience with advanced technology nodes is an added advantage.
Tools & Technologies
Verilog/SystemVerilog
Synopsys/Cadence/Mentor tools
SpyGlass
Design Compiler
PrimeTime
Questa/VCS/Xcelium
Perl/Python/Tcl
Key Competencies
Strong RTL coding expertise
Problem-solving and debugging skills
Strong understanding of SoC architecture
Ownership mindset
Effective collaboration across engineering teams
Attention to detail and quality-focused execution
Required Skills:
ASIC RTL Coding design
