Analog Design Engineer- eInfochips

Analog designer with experience of 5 to 8 Years of experience in below

CT sigma delta ADC RFIC design: LNA and mixer PLLs

Circuit Architecture & Design: Architect and design high-performance analog/mixed-signal building blocks (e.g. PLLs ADCs/DACs RFIC).

EDA exposure: Custom Design/Schematic: Cadence Virtuoso (ADE/Maestro). Simulation: Spectre HSPICE or CustomSim. Physical Verification: Mentor Calibre (DRC/LVS/PEX) or Synopsys IC Validator. Reliability/Sign-off: Experience with Voltus RedHawk or similar power/IR integrity tools

Multi-Node Design: Translate and optimize designs across different process geometries including transition strategies from Planar (e.g. 28nm) to FinFET (e.g. 16nm 7nm) nodes.

Simulation & Verification: Perform comprehensive pre-layout and post-layout simulations including Monte Carlo corner analysis noise analysis and reliability modeling (EM/IR/Aging/BTI/HCI).

Methodology: Drive best practices in analog design methodology including the adoption of automated design tools and script-based verification (Python/SKILL/Tcl).