Fiveforce Techno Solutions

Job Description or in Computerss/Electronics/Electrical Engineering with minimum of 4 years of strong hands on block/sub HM level Timing closure or chip top level timing closure. Should have experience in 28nm below technologies experience in 10nm below is an added advantage Should المزيد...

Mandatory Skills:Automated TestingMicrosoft Azure Cloud PlatformPL/SQL programmingPython TestingMandatory Skills Description:Bachelors Degree in IT Business Computer Science or a related field Software Quality Assurance professional with 5 years experienceExtensive experience with ETL المزيد...

OverviewThe Physical Design Engineer with PNR (Place and Route) expertise plays a critical role in the semiconductor industry responsible for transforming netlist descriptions into physical representations suitable for silicon fabrication. This position is fundamental for ensuring tha المزيد...

Responsibilities:* Responsible for leading a team of STA engineers and closing highfrequency lowertech node complex designs.* Conduct fullchip timing analysis from early investigation to final implementation and tapeout.* Propose or develop timing methodologies to support the timing f المزيد...

KEY RESPONSIBLITIES:* Drive full chip IR/EM convergence on multiple ASICs across different technology nodes.* Work closely with architecture power management package and floorplan team to come up with robust power delivery design.* Work with RTL and PD team in coming up with the low p المزيد...

Key ResponsibilitiesDevelop and execute fullchip floor plan strategies.Collaborate with design teams to define chip architecture.Ensure proper placement of functional blocks based on area power and performance constraints.Perform timing analysis to meet synchronization requirements.Co المزيد...

Job Title : PD TileLocation : Bangalore This role is for a PD Tile with 3 years of experience focusing on blocklevel physical design and understanding the entire PnR cycle. The candidate should have handson experience with industrystandard tools like ICC2/Innovus for physical design المزيد...

ASIC (SoC) Verification EngineerJOB OVERVIEW : Expert in ASIC verification SV UVM and protocols like PCIe USB and Ethernet. Experienced in formal verification mixedsignal simulations and poweraware simulations. Skilled in functional/gatelevel simulations creating verification plans an المزيد...

Position Name AMS VerificationExperience Required: Minimum 4 years relevant experience is required.Overview With 4 years in ASIC SoC Verification (SV UVM) and 2 years in AMS Verification responsibilities include creating testbenches running simulations with Cadence Virtuoso and Spec المزيد...

Job Position Emulation EngineerOverview Experienced in emulation platforms (Palladium Veloce Zebu) Verilog VHDL C/C and System Verilog. Skilled in scripting (Perl Python Makefile) and waveform debug (Verdi/SimVision). Familiar with protocols like PCIE USB DDR and SPI. Strong communi المزيد...

Position Name Low Power SoC Verification Experienced in ASIC/SoC verification with 4 years focusing on lowpower design. Proficient in SV UVM poweraware simulation and tools like Synopsys Cadence and Mentor for power analysis. Skilled in lowpower design techniques (e.g. clock gating المزيد...

KEY RESPONSIBILITIES Tool Integration Code line Integration (the code line will have a mix of components written in C Verilog System Verlig Perl Python Ruby etc ; Porting Code from previous project and Devops related work. Machine Learning: Should be able to handle la المزيد...