Associate Hardware Engineer

• Develop and optimize custom layout implementations for IO (GPIO Peripheral IO) Power and Hard Macro IPs on advanced semiconductor technologies (e.g. TSMC GlobalFoundries...) working closely with technical experts from both Japan and Vietnam teams.
• Perform full-custom layout design for IO circuits analog circuits and low-power control circuits from schematic implementation through final layout release ensuring compliance with IP specifications and quality requirements.
• Conduct floorplan device placement routing and layout optimization of hierarchical IP blocks while adhering to technology design rules quality assurance standards and manufacturability requirements.
• Ensure designs achieve targets for performance power area reliability ESD robustness and silicon manufacturability.
• Execute physical verification activities including DRC LVS ERC Antenna and related validation checks and perform root-cause analysis and debugging of verification issues.
• Generate and maintain IP deliverables and library collateral including GDSII CDL LEF Liberty NDM and associated documentation required for downstream implementation flows.
• Collaborate with Chip Top Product and Physical Design teams to support integration verification and PPA (Performance Power Area) optimization at the chip level.
• Analyze and address reliability concerns including ESD Electromigration (EM) IR Drop and Latch-up throughout the IP development cycle.
• Drive productivity and quality improvements through methodology enhancement automation development and continuous process optimization.

Qualifications :

• Bachelors degree in Electronics Engineering Electrical Engineering Microelectronics Computer Engineering or related fields.
• Strong Academic background in semiconductor devices ability to understand and analyze the physical behavior of CMOS circuits parasitic effects signal propagation power distribution and ESD protection mechanisms is highly desirable.
• Strong foundation in engineering physics and mathematics. Familiar with fundamental concepts such as Ohms Law Kirchhoffs Current and Voltage Laws (KCL/KVL) current flow voltage resistance capacitance and basic semiconductor physics.
• Demonstrated interest in semiconductor IP development including circuit design physical implementation characterization library development and chip integration.
• Familiarity with EDA tools is a plus (Cadence Virtuoso Synopsys Siemens/Mentor etc.).
• Knowledge of Linux/Unix operating systems and scripting languages (Shell Python Perl Tcl) is an advantage.
• Strong analytical and problem-solving skills.
• Willingness to learn advanced semiconductor technologies and design methodologies.
• Good communication and teamwork skills in a multicultural environment.
• Ability to work independently as well as collaboratively within global engineering teams.
• Good English reading and communication skills.

Additional Information :

Renesas is an embedded semiconductor solution provider driven by its Purpose To Make Our Lives Easier. With a global team of over 21000 engineers and problem solvers in more than 30 countries we offer the opportunity to work on worldleading technology for Automotive Industrial Infrastructure and IoT shaping a safer healthier greener and smarter future.

At Renesas TAGIE is our culture grounded in being Transparent Agile Global Innovative and Entrepreneurial. It shapes how we work grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.

We believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.

Are you ready to join our team and shape the future with us

Renesas Electronics is an equal opportunity and affirmative action employer committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex race religion national origin gender gender identity gender expression age sexual orientation military status veteran status or any other basis protected by law. For more information please read our Diversity & Inclusion Statement.

Remote Work :

No

Employment Type :

Full-time