VLSI CAD Engineer

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APPLE INC has the following available in Cupertino California and various unanticipated locations throughout the USA. Support and enhance the Apple synthesis flow by optimizing processes and resolving any CAD tool issues that arise during the synthesis of System-on-Chip (SoC) partitions; Work with industry-standard Electronic Design Automation (EDA) tools such as Cadence Genus and leveraging the Tel scripting language to fine-tune the synthesis flow ensuring efficient and robust design implementation; Engage in a proactive approach to troubleshooting debugging and refining synthesis methodologies to maintain seamless functionality within the Apple silicon design framework; Validate and improving features that contribute to Power Performance and Area (PPA) enhancements; Collaborate with the vendor team to refine and optimize these features aligning them with the unique requirements of Apple silicon; Perform an in-depth analysis of how each feature impacts PPA metrics allowing for the identification of optimization opportunities; Perform continuous monitoring and evaluation of the effectiveness of these enhancements which help ensure that Apples synthesis and design methodologies remain efficient and tailored to the evolving needs of high-performance SoC designs; Conduct Synthesis and Place-and-Route (PnR) experiments on various SoC partitions to assess and validate new design features before incorporating them into production workflows; Leverage a strong understanding of Register Transfer Level (RTL) design and an analytical approach to evaluating the effects of different plugins and attributes on design metrics; Extend synthesis experiments through the PnR stage which ensures that the correlation of Power Performance and Area (PPA) remains consistent across different design phases; Ensure the post-synthesis and post-PnR results are well-aligned which leads to an accurate and efficient implementation in final production-ready designs; Collaborate with cross-functional teams such as the Logic Equivalence (LEQ) team to validate new features after synthesis; Ensure the synthesized design maintains logical equivalence with the original RTL; Develop automation scripts using Python to further streamline the synthesis workflow which significantly reduces manual intervention and improves overall productivity. 40 hours/week. At Apple base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $148987 - $194700/yr and your base pay will depend on your skills qualifications experience and location. nnPAY u0026 BENEFITS: Apple employees also have the opportunity to become an Apple shareholder through participation in Apples discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards and can purchase Apple stock at a discount if voluntarily participating in Apples Employee Stock Purchase Plan. Youll also receive benefits including: Comprehensive medical and dental coverage retirement benefits a range of discounted products and free services and for formal education related to advancing your career at Apple reimbursement for certain educational expenses including tuition. Additionally this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits: Apple benefit compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.

Masters degree or foreign equivalent in Electrical Engineering or related and/or experience must include:nnUsing synthesis EDA tool EDA tool optimization and CAD tool troubleshooting to achieve timing closure resolve quality-of-results issues and improve design convergence across multiple process nodesnUtilizing scripting languages for synthesis flow automation including fine-tuning design implementation workflowsnUsing scripting tools for automation development including creating utilities and streamlining synthesis workflowsnExperience with System-on-Chip (SoC) methodology Place-and-Route (PnR) experimentation and validation of design features to verify physical implementation feasibility ensure design integrity and optimize floor planning strategiesnUsing Register Transfer Level (RTL) design analysis to evaluate design metrics and correlation analysisnUtilizing Power Performance and Area (PPA) optimization feature validation and enhancing automation flows to meet product specifications reduce power consumption and maximize performance within area constraintsnUsing Logic Equivalence Checking (LEC) validation methods and cross-functional collaboration for design verificationnUsing post-synthesis and post-PnR correlation analysis to ensure accuracy in production-ready designsnUtilizing synthesis methodology development and refinement for proactive troubleshooting and debugging approach

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