Verification Platform Engineer, Platform Architecture

Apples Platform Architecture group develops the next generation of Apple hardware and the tools to make it possible. Our team builds high-performance verification systems that accelerate the development of Apple silicon. We aim to push the boundaries of pre-silicon validation with simulation solutions that apply and extend principles from hardware emulation.

This role bridges Apples next-generation platform technology with DV methodology and are seeking an engineer with background in Design Verification who is interested in cutting-edge verification techniques and comfortable rapidly prototyping this role you will enable transformational improvements to simulation throughput for DV workflows through testbench design infrastructure improvements and platform Ru0026D.

Own engagements with silicon engineering groups to evaluate integrate and maintain high performance RTL simulation testbench and design RTL for tool compatibility and simulation internal and external EDA tools (e.g. RTL simulation tools Logic Equivalence Checking LEC wave dumps design libraries) to diagnose issues and explore design and integrate infrastructure improvements for faster simulation turnaround after RTL closely (or embed) with internal teams for focused high-impact travel (approximately once a year) to collaborate with development groups within the US.

Bachelors degree in Computer Engineering Electrical Engineering or a related field (or equivalent practical experience).nExperience with SystemVerilog and EDA with software development (e.g. using C) and scripting (e.g. Perl or Python).

Masters degree in Computer Engineering Electrical Engineering or another hardware-related field.n3 years of relevant hands-on experience in Design Verification methodologies (UVM DPI-C testbench architecture). nExperience applying LEC linting / static analysis tools waveform debugging and simulation / emulation understanding of SystemVerilog simulation semantics (events time glitches); intuitive grasp for hardware representation (clocks resets latches).nStrong communication skills with a proven history of cross-functional collaboration across silicon engineering design verification and EDA development teams and organizational boundaries. nExperience with software optimization high-performance computing (HPC) co-simulation architectures or hardware acceleration / of agentic pipelines graphs skills or similar work enabling AI productivity for other engineers.