Standard Cell Design Methodology & Flow Engineer

Do you have passion to join a world-class Digital Design Engineering group and take imaginative and revolutionary ideas and determine how to turn them into reality! You will apply engineering fundamentals and start from scratch if needed bringing forward-thinking and groundbreaking ideas to the real world. Youll help design the tools that allow us to bring customers experiences theyve never-before envisioned. We have an extraordinary opportunity for Standard Cell Design Methodology and Flow this highly visible role you will be at the heart of a processor design effort working with the custom digital circuits team and library development making a critical impact in delivering quality products to market quickly.

Imagine yourself at the center of our cutting-edge processor design in deep submicron technologies and on standard cell library designs. You will have the opportunity to integrate and come-up with new insights as well as work with a team of talent this role on our custom circuits team you will:n- Be the interface to internal CAD team for planning production flows and with foundry on PDK requirements.n- Collaborate with technology team on new process requirements and work with design/CAD team to enable relevant tools/flowsn- Implement sophisticated digital block in Verilog/SystemVerilog run simulations or formal check for verification.n- Use data analysis techniques and/or sophisticated Machine Learning models to study the circuit trends in timing power and area and to potentially detect quality issues in large datasets.

BS and a minimum of 10 years of relevant industry experience

At least 5 years in Library Characterization Timing/Power/CCS Noise/Variation Modeling Liberty Formats Spice simulation Static Timing and Power Analysis flows etc. nExperience with timing modeling of large custom macros and complex sequential to Design For Test scan concept and write DFT friendly RTLnUnderstands all aspects of implementation specification design timing power and flow analysis and ML knowledge to study data trend and perform QA on big dataset with automationnFlow automation skills in standard cells development and integration to improve execution efficiency. Experience of using Python/TCL/PerlnKnowledge of FE modeling/Verilog and/or VHDL and experience with various EDA tools for characterization synthesis place-route Verilog simulation spice simulation formal verification DRC/LVS RC extraction and/or library characterization. nProven understanding of device physics and with foundry ecosystem and benchmarking practice.