Staff Engineer, SRAM Circuit Design

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What Youll Do

We are looking for a passionate and experienced Staff Engineer SRAM Circuit Design to lead the development of next-generation SRAM this position you will drive end-to-end design of high-performance low-power memory circuits used in cutting-edge semiconductor products. Your work will directly influence the power performance and area (PPA) efficiency of future computing mobile and AI platforms.

This role combines deep technical expertise with strategic team leadership offering the opportunity to innovate at the forefront of semiconductor design.

• Design and develop SRAM memory arrays including bit cells sense amplifiers decoders and control circuits for advanced process nodes (e.g. 2nm 3nm and 5nm).
• Optimize SRAM designs for performance power and area (PPA) and yield.
• Develop custom layouts and perform physical design verifications (e.g. DRC LVS).
• Evaluate trade-offs between speed power and area to meet design targets.
• Develop and improve SRAM design methodologies including automation scripts for design simulation and verification.
• Work with product and test engineers to develop test plans and support silicon bring-up.
• Mentor Junior engineers providing guidance on SRAM design techniques and best practices.
• Perform extensive circuit simulations using tools like HSPICE finesim or cadence Spectre to validate SRAM functionality and performance.
• Contribute to patents technical papers or industry conferences to advance SRAM technology.

What You Bring

• Bachelors degree in electrical engineering with 10 years of industry experience or masters degree in electrical engineering with 8 years of experience strongly preferred.
• Prior experience in SRAM or memory circuit design with a proven track record of delivering SRAM designs in advanced process nodes.
• Strong understanding of semiconductor devices physics and process technology (FinFET GAA SOI etc.).
• Expertise in SRAM architecture including bitcells sense amplifiers write drivers and read/write control paths.
• Familiarity with timing analysis power analysis and design for manufacturability (DFM).
• Proficiency in circuit simulation variation analysis and design tools such as Spectre HSPICE Cadence Virtuoso etc.
• Knowledge of scripting languages (e.g. Python Perl TCL) for automation of design tasks.
• Strong cross-functional collaboration and communication skills for working with design layout verification and technology development teams.
• Experience with advanced technology nodes (e.g. 5nm 3nm or beyond).
• Knowledge of SRAM compiler development and experience with low-power SRAM design techniques (e.g. power gating voltage scaling).
• Background in silicon debug and root-cause analysis.
• Youre inclusive adapting your style to the situation and diverse global norms of our people.
• An avid learner you approach challenges with curiosity and resilience seeking data to help build understanding.
• Youre collaborative building relationships humbly offering support and openly welcoming approaches.
• Innovative and creative you proactively explore new ideas and adapt quickly to change.

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