Staff Engineer AIML

About MIPS @ GlobalFoundries:
GlobalFoundries is a leading full-service semiconductor foundry providing a unique combination of design development and fabrication services to some of the worlds most inspired technology companies.
With the addition of the MIPS team GF now offer a rich portfolio of RISC-V CPUs especially AI-enabled processors for the Physical AI world.

Summary of Role:
We are seeking an experienced CPU IP Design Engineer. Responsible for Defining leading and owning RTL development of our latest AI-enabled RISC-V CPU core. The candidate will be responsible for all aspects of the design including Functional Features Performance Power and Area.

Essential Responsibilities:
Drive the micro-architecture and design of critical blocks of the CPU core
Design of RISC-V Vector CPU core and its custom extensions
Design of AI-enabled Matrix engine to augment the Vector CPU
Explore high-performance strategies working with the CPU modeling team
Perform Microarchitecture development and specification- from early high-level architectural exploration through microarchitectural research and arrive at detailed specifications
Configure Design Features Development assessment and refinement of RTL design to target power performance area and timing goals
Perform Functional verification support and assist in the design verification strategy
Assist with the verification of RTL design performance goals
Partner with a multi-functional engineering team to implement and validate physical design aspects of timing area reliability testability and power

Other Responsibilities:
Perform all activities in a safe and responsible manner and support all Environmental Health Safety & Security requirements and programs.

Required Qualifications:
Hands-on working knowledge of the pipeline stages of an in-order or out-of-order high-performance CPU core
Thorough knowledge of microprocessor architecture including expertise in one or more of the following areas:
* Instruction fetch and decode branch prediction techniques
* Instruction scheduling register renaming Reorder Buffer (ROB)
* Out-of-order execution
* Integer and Floating-point execution
* Load/Store execution
* Instruction and Data Prefetch
* Vector data path
* Cache and memory subsystems
Knowledge of Cache coherency and memory consistency
Knowledge of System Verilog Verilog and/or VHDL
Experience with simulators and waveform debugging tools.
Knowledge of logic design principles along with timing and power implications
Masters with 4-7 years of experience PhD 2-5 years of work experience

Preferred Qualifications:
Experience with designing RISC-V ARM and/or MIPS CPU
Experience with Hardware multi-threading virtualization and SIMD designs
Experience with vector and matrix-enabled CPUs preferably RISC-V processors.
Understanding of high-performance techniques and trade-offs in a CPU microarchitecture
Understanding of low-power microarchitecture techniques
Experience using a scripting language such as Perl or Python
Understanding of CPU integration at SoC level
Understanding of Safety and Security microarchitecture

Expected Salary Range

The exact Salary will be determined based on qualifications experience and location.