SoC Physical Design Engineer, STATiming
San Jose, CA - USA
Job Summary
- Work with design teams to understand and debug constraints and facilitate logic changes to improve timing.n- Work with the Physical Design team highlighting issues and best practices.n- Help create timing ECOs for project tapeout.n- Create and maintain scripts and methodologies for analysis and runs.n- Create documentation and help with guidelines/specs.n- Deep analysis of timing paths to identify key issues.n- Implement timing infrastructure.
Minimum BS and 3 years of relevant industry with large design STA and Timing skills with Perl and TCL.
Hands-on experience in with important aspects of timing of large high-performance SoC designs in sub-micron in STA and methodologies for timing closure and have a fundamental understanding of noise crosstalk and OCV effects among with circuit modeling including SPICE models and worst-case corner with ECO techniques and communicator who can accurately describe issues and follow them through to completion.
Required Experience:
IC
About Company
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