SoC Physical Design Engineer, PnR

Imagine what you could do here! At Apple new ideas have a way of becoming extraordinary products services and customer experiences very quickly. Bring passion and dedication to your job and theres no telling what you could accomplish. Dynamic hardworking people and inspiring innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver the next groundbreaking Apple product!nnIn this visible role you will be directly responsible for the physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC utilizing innovative process technology.

Work with the logic design team to understand partition architecture and drive physical aspects early in the design cycle.n Complete netlist to GDS2 implementation for partition(s) meeting schedule and design goals.n Timing physical and electrical verification and driving the signoff closure for the partitions.n Resolve and improve design and flow issues related to physical design identify potential solutions and drive execution. n Drive optimization of PnR partitions to achieve best Power/Performance/Area.

Minimum BS and 10 years of relevant industry experiencenExperience with partition level Pu0026R implementation including floorplanning clock and power distribution timing closure physical and electrical verificationnExperience with physical design construction and analysis flows and methodology

MS in Electrical/Electronics/Computer Engineering or related fieldnExperience with large SOC designs (u003e20M gates) with frequencies in excess of 1GHZnFamiliar with various process-related design issues including Design for Yield and Manufacturability and multi-vt strategiesnExperience with industry standard tools understanding their capabilities and underlying algorithmsnExperience with typical SOC issues such as multiple voltage and clock domains and mixed signal block integrationnFrom a CAD perspective experience with floorplanning tools Pu0026R flows global timing verification and physical design verification flowsnAbility to adhere to stringent schedule and die size requirementsnStrong communication skills