Signal and Power Integrity (SIPI) Engineer (SMES)

Job Title: Signal and Power Integrity (SI/PI) Engineer (SMES)

Job Code: 46286

Job Location: Camden NJ (on-site)

Schedule: 9/80 Regular (every other Friday off)

Job Description:

L3Harris Integrated Systems & Encryption (IS&E) is a recognized global leader in the design development and production of secure communication systems and products supporting mission-critical space ground air and naval operations. L3Harris IS&E is where employees have the opportunity to make a significant impact on our business and the world around us while thriving in an environment that continually fosters growth and career development. We are committed to providing best-in-class solutions to our customers with the highest level of integrity excellence and uncompromised quality in everything we do. L3Harris offers a flexible working environment where contributions are recognized and rewarded

The Signal and Power Integrity (SI/PI) Engineer is responsible for ensuring the electrical integrity of high-speed digital and analog signals across complex PCB designs and for maintaining clean stable power delivery to all circuitry within defined performance specifications. This role requires deep expertise in SI/PI analysis methodologies and simulation tools and directly impacts the reliability and performance of advanced communication systems developed for National Security applications.

Essential Functions:

Perform SI/PI analysis for PCB designs
Leverage prior experience in digital circuitry design and signal integrity analysis methods to analyze digital CCAs using analysis tools such as HyperLynx HFSS and SIwave
Generate guidelines for layout and stack-up to ensure compliance with timing and signal quality specs
Develop and validate IBIS models for accurate pre- and post-layout simulation
Conduct power integrity analysis; minimize power rail noise voltage droop and power plane resonance
Ensure power delivery network (PDN) stability across relevant frequency ranges including target impedance analysis
Optimize PCB interconnects to support the high speed demands of PCIe Gen 4/5 DDR4/5 LPDDR4/5.
Model and analyze SERDES interfaces
Actively participate in peer and formal design reviews evaluating root cause signal/power issues
Validate and debug designs in the lab as required
Work closely with layout engineers applying knowledge of PCB stack-up and high-speed layout constraints
Generate technical documentation and reports with SI/PI findings and recommendations

Qualifications:

Active SECRET Clearance
Bachelors Degree in Electrical Engineering or related field with 6 years of relevant experience or a Masters Degree with 4 years specializing in digital Circuit Card Assembly (CCA) design and SI/PI analysis using commercial tools (e.g. HyperLynx Ansys SIwave).
Understand transmission line theory impedance matching crosstalk reflection jitter
Ability to model and analyze high-speed interconnects
Familiarity with PCB fabrication and materials and how they impact high-speed digital design
Strong analytical debug and problem-solving skills
Strong logic/PCB debug and analytical skills.
Ability to collaborate with cross-functional teams (Components Engineering ECAD PCB design engineers RF engineers mechanical engineering systems engineering software engineering and factory personnel)
Excellent written verbal and presentation skills with ability to clearly communicate technical findings

Preferred Additional Skills:

Experience in Aerospace / Defense
Experience using the following tools: Xpedition HyperLynx Ansys SIwave HFSS
S-parameter modeling
Experience with industry standards (JEDEC IEEE)
Experience with Earned Value Management

In compliance with pay transparency requirements the salary range for this role is $93341 - $156188. This is not a guarantee of compensation or salary as final offer amount may vary based on factors including but not limited to experience and geographic location. L3Harris also offers a variety of benefits including health and disability insurance 401(k) match flexible spending accounts EAP education assistance parental leave paid time off and company-paid holidays. The specific programs and options available to an employee may vary depending on date of hire schedule type and the applicability of collective bargaining agreements.

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