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Senior SerDes & Analog Layout Design Engineer

Microsoft

Job Location:

Raleigh, WV - USA

Yearly Salary: USD 119800 - 234700

Posted: 5 October 2026 (Yesterday)

Application Deadline: 2 January 2027

Vacancies: 1 Vacancy

Job Summary

Overview

Microsoft Silicon Cloud Hardware and Infrastructure Engineering (SCHIE) is the team behind Microsofts expanding Cloud Infrastructure and responsible for powering Microsofts Intelligent Cloud mission. SCHIE delivers core infrastructure and foundational technologies supporting Azure Microsoft 365 Teams Xbox and next-generation AI platforms at hyperscale with a focus on high-quality efficient and trusted cloud hardware solutions.

As Microsofts cloud and AI businesses continue to grow high-speed die-to-die (D2D) connectivity is critical to delivering scalable power-efficient custom silicon. The Semi & Custom IP team develops advanced analog and mixed-signal IP including D2D SerDes interfaces for next-generation AI accelerators cloud infrastructure and custom silicon platforms powering Microsofts future AI services and datacenter offerings.

We are looking for a Senior D2D SerDes & Analog Layout Design Engineer to be a hands-on technical contributor and layout lead for matching-critical analog and D2D SerDes physical implementation. This high-visibility role will own complex subsystem deliverables guide layout execution and technical reviews collaborate across design and integration teams and drive production-ready IP from planning through tapeout. The position offers opportunities to broaden technical scope deepen D2D and advanced-node expertise and grow technical leadership through direct work on strategic silicon programs.

#SCHIE

Responsibilities

Drive physical implementation of complex D2D SerDes and analog/mixed-signal IP in advanced process technologies from floorplanning through tapeout signoff and integration.
Own or co-own top-level D2D analog front-end floorplanning and integration including partitioning hierarchy die-edge constraints bump or micro-bump alignment ESD interfaces power distribution sensitive routing and package-aware implementation tradeoffs.
Establish matching and parasitic-control strategies for critical circuits using symmetry common-centroid placement interdigitation device orientation control dummy structures shielding guard rings isolation return-path planning and gradient mitigation.
Help lead D2D layout execution across multiple blocks and contributors by defining implementation plans coordinating technical work reviewing layouts resolving cross-block dependencies and supporting milestone closure.
Partner with circuit design leadership to translate electrical requirements into physical implementation constraints and make layout-versus-circuit tradeoffs that improve system-level power performance area signal integrity reliability and yield.
Identify and resolve layout risks for high-speed transmitter receiver clocking bias equalization PLL/DLL and related analog front-end circuitry.
Collaborate across signal integrity package ESD physical design CAD foundry reliability and SoC teams to align interface definitions and integration requirements for the assigned subsystem.
Own physical verification and signoff closure including DRC LVS ERC antenna density extraction review EMIR reliability analysis layout-dependent effects and complex cross-hierarchy debug.
Contribute to layout quality criteria review checklists release requirements and signoff evidence for internally and externally developed D2D and analog IP.
Deliver production-ready IP collateral including GDS/OASIS LEF abstracts integration views interface documentation waiver rationale review records and signoff packages for SoC and package integration.
Develop and improve analog layout methodologies reusable templates automation flows and productivity solutions using SKILL TCL Python or similar scripting languages.
Provide technical guidance and mentorship through design reviews coaching documentation and sharing of advanced-node analog and D2D layout practices.
Coordinate technical execution with contractors vendors and geographically distributed design partners by setting expectations reviewing quality resolving issues and supporting program commitments.
Communicate technical status risks tradeoffs and recommendations to engineering and program stakeholders for assigned D2D deliverable

Qualifications

Required Qualifications:

Doctorate in Electrical Engineering Computer Engineering Computer Science or related field AND 1 year(s) technical engineering experience OR Masters Degree in Electrical Engineering Computer Engineering Computer Science or related field AND 4 years technical engineering experience OR Bachelors Degree in Electrical Engineering Computer Engineering Computer Science or related field AND 5 years technical engineering experience OR equivalent experience.

Other:

Ability to meet Microsoft customer and/or government security screening requirements is required for this role. These requirements include but are not limited to the following specialized security screening:Microsoft Cloud Background Check. This position is required to pass the Microsoft Cloud Background Check upon hire or transfer and every two years thereafter.

This role will require access to information that is controlled for export under export control regulations potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations the EU Dual Use Regulation and/or other export control a condition of employment the successful candidate will be requiredto provide either proof of their country of citizenship or proof of their U.S. permanent residency or other protected status(e.g. under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled meet this legal requirement and as a condition of employment the successful candidates citizenship will be verified with a valid passport. Lawful permanent residents refugees and asylees may verify status using other documents where applicable.

Preferred Qualifications:

5 years of analog or mixed-signal layout experience including matching-critical transistor-level layout in advanced process technologies.
Experience owning significant analog or mixed-signal layout deliverables through physical verification signoff and tapeout.
Experience using Cadence Virtuoso and Siemens/Mentor Calibre physical verification tools.
Experience with DRC LVS ERC antenna extraction-aware layout and advanced-node physical signoff.
Experience collaborating across circuit design and physical implementation teams and providing technical guidance or design reviews to other layout contributors.
Experience with high-speed SerDes D2D interfaces or comparable high-performance analog/mixed-signal IP including transmitter receiver clocking bias equalization PLL/DLL or related circuitry.

Deep understanding of analog matching symmetry layout-dependent effects device orientation process gradients coupling isolation shielding return paths and parasitic optimization.
Familiarity with D2D standards or implementations such as UCIe BoW or proprietary die-to-die links.
Experience with advanced packaging and chiplet integration including die-edge planning bump or micro-bump interfaces ESD structures package escape power delivery and signal-integrity constraints.
Experience influencing floorplan interface or circuit decisions based on physical implementation feasibility and extracted-layout results.
Experience leading top-level assembly and verification of analog subsystems containing blocks developed by multiple engineers or external partners.
Experience with EMIR and reliability signoff using Ansys Totem Cadence Voltus or equivalent tools.
Experience with Cadence automated place-and-route (APR) flows including floorplanning placement clock or signal routing physical optimization and integration of custom analog or mixed-signal IP with digitally implemented logic.
Experience with FinFET and/or Gate-All-Around technologies and advanced nodes such as 5nm 3nm or beyond.
Demonstrated ability to mentor engineers lead technical reviews and resolve complex layout issues across team boundaries.
Experience managing technical execution with geographically distributed teams contractors vendors or design-service partners across multiple milestones or programs.

#SCHIE

Silicon Engineering IC4 - The typical base pay range for this role across the U.S. is USD $119800 - $234700 per year. There is a different range applicable to specific work locations within the San Francisco Bay area and New York City metropolitan area and the base pay range for this role in those locations is USD $160200 - $261000 per year.

Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:
position will be open for a minimum of 5 days with applications accepted on an ongoing basis until the position is filled.

Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age ancestry citizenship color family or medical care leave gender identity or expression genetic information immigration status marital status medical condition national origin physical or mental disability political affiliation protected veteran or military status race ethnicity religion sex (including pregnancy) sexual orientation or any other characteristic protected by applicable local laws regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process read more about requesting accommodations.

Required Experience:

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