Senior Physical Design Engineer

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Advancing the Worlds Technology Together

Our technology solutions power the tools you use every day--including smartphones electric vehicles hyperscale data centers IoT devices and so much more. Here youll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of whats possible and powering the future.

We believe innovation and growth are driven by an inclusive culture and a diverse workforce. Were dedicated to empowering people to be their true selves. Together were building a better tomorrow for our employees customers partners and communities.

The AGI (Artificial General Intelligence) Computing Lab is dedicated to solving the complex system-level challenges posed by the growing demands of future AI/ML workloads. Our team is committed to designing and developing scalable platforms that can effectively handle the computational and memory requirements of these workloads while minimizing energy consumption and maximizing performance. To achieve this goal we collaborate closely with both hardware and software engineers to identify and address the unique challenges posed by AI/ML workloads and to explore new computing abstractions that can provide a better balance between the hardware and software components of our systems. Additionally we continuously conduct research and development in emerging technologies and trends across memory computing interconnect and AI/ML ensuring that our platforms are always equipped to handle the most demanding workloads of the future. By working together as a dedicated and passionate team we aim to revolutionize the way AI/ML applications are deployed and executed ultimately contributing to the advancement of AGI in an affordable and sustainable manner. Join us in our passion to shape the future of computing!

Location: Daily onsite presence at our San Jose CA office / U.S. headquarters in alignment with our Flexible Work policy.

What Youll Do

• Own the physical implementation of memory-centric computing IP and SoC partitions from RTL netlist to GDSII including synthesis floorplanning placement clock tree synthesis (CTS) and routing.
• Drive block- and full-chip-level PPA (performance power and area) convergence and timing closure across multiple process corners and operating modes.
• Develop floorplans power delivery networks and macro placement strategies for memory controllers NoC and high-bandwidth interconnect subsystems.
• Perform static timing analysis (STA) constraint development and signoff resolving setup/hold timing IR-drop electromigration and signal integrity issues.
• Execute physical verification and signoff (DRC LVS antenna and reliability checks) in collaboration with foundry and standard-cell/memory library teams on advanced process nodes.
• Collaborate with RTL and verification engineers providing physical feedback that informs design-for-PPA and floorplan-aware microarchitecture decisions.
• Make design decisions out of a large design trade-off space across performance power thermal and cost.
• Develop and automate physical implementation flows and methodologies using Tcl/Python scripting and agentic AI tools and frameworks to improve turnaround time and quality of results.
• Communicate effectively with stakeholders including users partners and management to ensure that the designs are delivered on time and within budget.
• Complete other responsibilities as assigned.

What You Bring

• Bachelors with 5 years or Masters with 3 years or PhDs with 0 years of industry experience.
• Strong background in digital physical design and VLSI implementation.
• 5 years of experience in physical design implementation synthesis floorplanning place-and-route clock tree synthesis and timing closure for complex ASIC/SoC designs.
• Proficiency with industry-standard EDA tools such as Synopsys Fusion Compiler/ICC2 Cadence Innovus PrimeTime and StarRC.
• Experience with static timing analysis and constraint (SDC) development low-power design (UPF/CPF) and power IR-drop and electromigration analysis.
• Experience with physical verification (DRC LVS antenna) and tapeout on advanced FinFET process nodes.
• Experience implementing memory controllers NoC or high-speed interconnect IP and full-chip SoC integration.
• Proficiency in scripting (Tcl Python or Perl) for physical design flow automation.
• Experience in AI/ML workloads.
• Strong analytical and problem-solving skills
• Excellent communication and interpersonal skills
• Ability to work independently and as part of a team
• Youre inclusive adapting your style to the situation and diverse global norms of our people.
• An avid learner you approach challenges with curiosity and resilience seeking data to help build understanding.
• Youre collaborative building relationships humbly offering support and openly welcoming approaches.
• Innovative and creative you proactively explore new ideas and adapt quickly to change.

Base Pay Range

$138000 - $206000 USD