Senior FPGA Design Engineer

USCs Information Sciences Institute (ISI) a unit of the universitys Viterbi School of Engineering is a world leader in the research and development of advanced information processing computing communications and artificial intelligence technologies. ISIs faculty professional staff and graduate students conduct extraordinary information sciences research at locations in Arlington Virginia; Marina del Rey California; and Waltham Massachusetts.

The Reconfigurable Computing Group at ISI develops computer architectures and design methods that make specialized hardware more adaptable efficient and trustworthy. Recent work combines FPGA prototyping ASIC design purpose-built electronic design automation tools and hardware-software co-design to advance rapidly reconfigurable processing for RF sensing and communications acceleration of fully homomorphic encryption and hardware security and assurance. The group builds and evaluates working systems develops the tools needed to program and verify them and collaborates across disciplines to move research toward operational use.

We are seeking a highly talented and motivated Senior FPGA Design Engineer to research and develop novel tools and techniques for assuring FPGA hardware. Working with research staff and technical collaborators the engineer will plan and execute specialized FPGA designs to assess device functionality and state; work directly with FPGA hardware and laboratory instrumentation to measure validate and analyze device characteristics; and identify plan and implement methods that extend commercial and open-source EDA tools with new assurance capabilities.

This position is based in Arlington VA. Hybrid work options are available

• Plan lead implement and verify specialized FPGA systems and RTL components in VHDL or Verilog to support hardware-assurance research.
• Use FPGA EDA tools to perform synthesis implementation timing analysis timing closure and device programming.
• Interface directly with FPGA hardware power supplies and other test instrumentation to collect measurements validate behavior and analyze device functionality and characteristics.
• Develop Python TCL and related scripts to automate design flows testing data collection and analysis.
• Identify plan and implement extensions to commercial and open-source EDA tools and evaluate new FPGA-assurance capabilities.
• Translate research concepts and project goals into technical plans implemented prototypes and independently developed system components working under minimal supervision.
• Document designs methods test results and technical progress; contribute to sponsor reports publications presentations and meetings with collaborators.
• Review technical implementations establish engineering best practices provide technical mentorship and guide junior researchers and engineers as needed.
• Stay current with FPGA architectures EDA methods hardware-assurance research and emerging AI-assisted design approaches relevant to project goals.

• Masters degree in computer engineering electrical engineering computer science or a closely related field.
• Eight or more years of overall relevant research engineering experience including at least five years of directly relevant FPGA design experience.
• Demonstrated experience planning and executing FPGA designs and developing RTL in VHDL or Verilog.
• Proficiency with scripting languages such as Python or TCL.
• Proficiency with FPGA EDA tools such as AMD Xilinx Vivado or Intel Altera Quartus including synthesis implementation and timing closure.
• Experience interfacing directly with FPGA hardware power supplies and other test instrumentation.
• Willingness and eligibility to apply for and maintain a Top Secret security clearance. Eligibility for this clearance requires U.S. citizenship.

• Ten or more years of relevant research engineering experience.
• Current Secret security clearance or higher.
• Experience applying large language model assisted design to FPGAs or implementing AI or machine learning workloads on FPGAs using AMD Vitis AI or Intel Altera FPGA AI Suite.
• Knowledge of FPGA architecture and device primitives including AMD Xilinx Zynq Virtex-7 UltraScale or Versal devices or comparable Intel Altera devices.
• Contributions to or experience with open-source EDA tools such as Google Project X-Ray VTR or VPR RapidSmith or TORC.
• Demonstrated use of revision-control systems such as Git or Mercurial in a multi-user project environment.

The annual base salary range for this position is $140000 to $ extending an offer of employment the University of Southern California considers factors such as but not limited to the scope and responsibilities of the position the candidates work experience education and training key skills internal peer equity federal state and local laws contractual stipulations grant funding and external market and organizational considerations.

• Work on exciting and engaging projects with real-world impact.
• Contribute across the full project lifecycle in a small-team environment.
• Enjoy a workplace that supports a quality work-life balance.
• Access opportunities for top-tier university education for you and your children.
• Receive comprehensive benefits from medical coverage to matched retirement contributions.

Addtional Education Requirements Combined experience/education as substitute for minimum education
Minimum Experience: 8 years

Minimum Skills: Knowledge of one or more relevant programming languages (e.g. Python C Goolang). Experience with Linux. Experience with Virtual LAN and/or Virtual Extensible LAN. Experience with Melanox Switches. Experience with SDN programming. Experience with Ansible Bash and Nagios. Experience with Prometheus. Familiarity with and Simple Network Management Protocol. Experience with applicable IT protocols (e.g. Border Gateway Protocol Secure Shell Transport Layer Security). Experience with iptables and Network File System. Excellent written and oral communication skills.
Preferred Education: Masters degree Masters degree

Preferred Experience: 10 years
Preferred Skills: Proven leadership ability. Experience in a university environment. Experience with artificial intelligence very large-scale integration design machine learning deep learning (e.g. TensorFlow PyTorch HuggingFace) and Dockerization.

USC is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race color religion sex sexual orientation gender identity national origin protected veteran status disability or any other characteristic protected by law or USC policy. USC observes affirmative action obligations consistent with state and federal law. USC will consider for employment all qualified applicants with criminal records in a manner consistent with applicable laws and regulations including the Los Angeles County Fair Chance Ordinance for employers and the Fair Chance Initiative for Hiring Ordinance and with due consideration for patient and student safety. Please refer to theBackground Screening Policy Appendix Dfor specific employment screen implications for the position for which you are applying.

We provide reasonable accommodations to applicants and employees with disabilities. Applicants with questions about access or requiring a reasonable accommodation for any part of the application or hiring process should contact USC Human Resources by phone at or by email at. Inquiries will be treated as confidential to the extent permitted by law.

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