Senior Engineer RTL Power Macro Modeling

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Role Summary

We are seeking an engineer to develop power and energy macromodels for die-to-die (D2D) PHY and 2.5D interposer interconnect in C-HBM programs. The role builds these models from S-parameter models of the interconnect calibrates them againstcircuit-level references and makes them fast enough to run over long workload traces. The resulting models feed time-indexed power maps into the trace-driven power and thermal simulation flow.

Location:Daily onsite presence at ourSan Jose CAin alignment with our Flexible Work policy

Reports to:SVP R&D (Power & Thermal Lab)

What Youll Do

• Develop energy and power macromodels of interposer interconnect and PHY transmit front-ends from S-parameter models of the channel.

• Extract per-lane self-capacitance and inter-lane mutual capacitance from the network parameters and relate them to switching energy.

• Build a circuit-level reference in SPICE and use it to calibrate the macromodels and bound their error.

• Develop and compare reduced-order model forms and select among them by measured accuracy.

• Design calibration stimuli and parameter-extraction procedures.

• Ensure models evaluate efficiently over wide buses and long workload traces.

• Analyze sensitivity to data pattern bus encoding activity factor and operating point.

• Extend the modeling approach to additional interfaces and interconnect structures as the program scope grows.

• Deliver validated models and regression checks into the trace-driven simulation pipeline and collaborate with software engineers on model interfaces.

What You Bring

• Bachelors degree with 5 years of experience or Masters degree with 3 years of experience preferred or PhD Degree with 0 years of experience.

• Strong Python for numerical and scientific computing.

  Proven self-discipline and professional maturity to execute independent research and meet rigorous milestones with a strong sense of accountability for both personal and collective goals in a fast-paced on-site environment.

• Familiarity with S-parameters and frequency-domain network analysis.

  Experience with SPICE-level circuit simulation.

• Understanding of dynamic switching power in CMOS drivers and interconnect including coupling capacitance.

• Ability to abstract circuit behavior into compact analytical or table-based models.

• Familiarity with RTL/SystemC simulation flows and how power models are used in them.

• Deep knowledge and experience in Thermal Engineering.
• Expertise in FloTHERM and familiarity with other CFD tools.
• Excellent technical writing and verbal communication skills for collaboration documentation and presentations.

Preferred Qualifications

• Exposure to UCIe or other die-to-die interfaces high-speed I/O or 2.5D packaging.

• Hands-on experience with power analysis tools such as PrimeTime PX StarRC or Verdi.

• Experience running large parameter sweeps or parallelized analysis.

• Prior experience in power or thermal modeling.

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