SEG PMU Engineer

Join our team at Apple developing complex digital IPs for Apples custom mixed-signal integrated circuits. We have already shipped hundreds of millions of chips into Apples existing product lines and are developing new chips for future product lines! As a member of our mixed-signal ASIC team you will be responsible for crafting sophisticated digital IPs for Apple power conversion and system management ICs. You will work with the system architects product teams verification engineers and analog designers in creating block level specifications and implementing the designs. You will own the creation of the blocks and take them through the concept implementation and validation phases and then into mass production. Learn and use state of the art digital ASIC development flows to implement your designs. nnWe supply silicon to Apples industry leading hardware development teams and collaborate closely with them. We have a close-knit prolific team looking to add enthusiastic digital design engineers to develop new ASIC IPs. We pride ourselves for being an especially diverse team that values new approaches to deliver creativity high productivity and industry leading results. Join us in building Apples next generation products. Do you want to be a part of building the surprise and delight in Apples future products

Deliver complex digital IPs meeting schedule area power and performance targets. n Collaborate in developing precise design specifications for digital control blocks. n Implement physical design ready blocks in System Verilog. n Collaborate with project leads to track progress and gauge tapeout readiness. n Work with DV teams to create verification plans. n Work with silicon validation team in developing lab validation and qualification plans.

Bachelors degree or higher in electrical engineering or computer with power estimation tools and with digital ASIC development flows and understanding of low power design techniques.

Experience developing digital IPs for SoCs or mixed signal track record of delivering quality designs on with synthesis and static timing in Clock Domain Crossing design and verification techniques.