RTL Engineer, Networking ASIC
Job Location:
Job Location:
San Jose, CA - USA
Monthly Salary:
Not Disclosed
Monthly Salary:
Posted on:
15 days ago
Posted on:
Vacancies:
1 Vacancy
Vacancies:
Job Summary
Job Description:
Our client is a Silicon Valley-based hardware startup pioneering infrastructure solutions that accelerate AI data centers to deliver Faster AI. Todays AI performance is frequently limited by communication bottlenecks.
Our client introduces multiple industry-first innovations across silicon packaging software and systems to deliver sharp performance improvements and greater GPU utilization speeding training job completion times and tokens-per-second for more profitable inference.
The companys solutions and value proposition are validated by leading hyperscalers.
Our client has raised over $200M including a recent Series A round. The company is led by a team of Silicon Valley executives who have delivered multiple product lines and led multiple companies to billion-dollar exits.
The company has a world-class engineering team with decades of experience in state-of-the-art silicon packaging optics software and systems.
Position Overview
We are seeking experienced RTL designers to help define and implement our industry-leading Networking ASICs. If youre a highly motivated self-starter eager to solve real-world problems this is a unique opportunity to shape the future of AI Networking. As part of the Design Group you will be responsible for defining specifying architecting executing and productizing cutting-edge Networking chips.
Responsibilities
Packet buffering queuing and scheduling: Work on micro architecture and design implementation of high-speed networking ASICs focusing on latency optimization and quality of service (QoS) support. Prior experience with on-chip memory subsystem and scheduling/arbitration desig
Implementation and Testing: Implement designs on ASIC platforms ensuring compliance with industry standards and performance benchmarks. Work with the verification team to conduct thorough testing and validation to ensure functionality and reliability.
Performance Optimization: Analyze and optimize pipelining architectures to improve performance metrics.
Protocol Support: Provide support for various networking protocols such as Ethernet and IP protocols and high-speed interconnects such as UCIe.
Troubleshooting and Debugging: Investigate and resolve complex issues related to packet queuing working closely with cross-functional teams including system architects hardware engineers and firmware developers.
Qualifications
ME/BE with a minimum of 8-15 years of experience.
Hands-on knowledge of System Verilog and Verilog is mandatory.
Solid understanding of ASIC design methodologies including simulation verification synthesis and timing adjustments.
Proven expertise in designing and optimizing scheduling and QoS mechanisms.
Experience with Ethernet and IP protocols.
Strong analytical and problem-solving abilities with meticulous attention to detail in troubleshooting and debugging complex networking issues.
Excellent verbal and written communication skills with the ability to collaborate effectively in a team environment and present technical information to diverse audiences.
Our client is a Silicon Valley-based hardware startup pioneering infrastructure solutions that accelerate AI data centers to deliver Faster AI. Todays AI performance is frequently limited by communication bottlenecks.
Our client introduces multiple industry-first innovations across silicon packaging software and systems to deliver sharp performance improvements and greater GPU utilization speeding training job completion times and tokens-per-second for more profitable inference.
The companys solutions and value proposition are validated by leading hyperscalers.
Our client has raised over $200M including a recent Series A round. The company is led by a team of Silicon Valley executives who have delivered multiple product lines and led multiple companies to billion-dollar exits.
The company has a world-class engineering team with decades of experience in state-of-the-art silicon packaging optics software and systems.
Position Overview
We are seeking experienced RTL designers to help define and implement our industry-leading Networking ASICs. If youre a highly motivated self-starter eager to solve real-world problems this is a unique opportunity to shape the future of AI Networking. As part of the Design Group you will be responsible for defining specifying architecting executing and productizing cutting-edge Networking chips.
Responsibilities
Packet buffering queuing and scheduling: Work on micro architecture and design implementation of high-speed networking ASICs focusing on latency optimization and quality of service (QoS) support. Prior experience with on-chip memory subsystem and scheduling/arbitration desig
Implementation and Testing: Implement designs on ASIC platforms ensuring compliance with industry standards and performance benchmarks. Work with the verification team to conduct thorough testing and validation to ensure functionality and reliability.
Performance Optimization: Analyze and optimize pipelining architectures to improve performance metrics.
Protocol Support: Provide support for various networking protocols such as Ethernet and IP protocols and high-speed interconnects such as UCIe.
Troubleshooting and Debugging: Investigate and resolve complex issues related to packet queuing working closely with cross-functional teams including system architects hardware engineers and firmware developers.
Qualifications
ME/BE with a minimum of 8-15 years of experience.
Hands-on knowledge of System Verilog and Verilog is mandatory.
Solid understanding of ASIC design methodologies including simulation verification synthesis and timing adjustments.
Proven expertise in designing and optimizing scheduling and QoS mechanisms.
Experience with Ethernet and IP protocols.
Strong analytical and problem-solving abilities with meticulous attention to detail in troubleshooting and debugging complex networking issues.
Excellent verbal and written communication skills with the ability to collaborate effectively in a team environment and present technical information to diverse audiences.
