Principal Design Verification Engineer Formal

Microsoft Silicon Cloud Hardware and Infrastructure Engineering (SCHIE) is the team behind Microsofts expanding Cloud Infrastructure and responsible for powering Microsofts Intelligent Cloud mission. SCHIE delivers the core infrastructure and foundational technologies for Microsofts over 200 online businesses including Bing MSN Office 365 Xbox Live Teams OneDrive and the Microsoft Azure platform globally with our server and data center infrastructure security and compliance operations globalization and manageability solutions. Our focus is on smart growth high efficiency and delivering a trusted experience to customers and partners worldwide and we are looking for passionate engineers to help achieve that mission.

The Compute Silicon & Manufacturing Engineering (CSME) organization within SCHIE is responsible for design development manufacturing and packaging of Microsofts state-of-the-art computer chips notably the Azure Cobalt. Our solutions provide sustainable strategic advantage to Microsoft and enable our customers to achieve more.

As Microsofts cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time in high volume with high quality and lowest cost is of paramount importance. To achieve this goal the Verification & Validation team is instrumental in defining and delivering operational measures of success for hardware manufacturing improving the planning process quality delivery scale and sustainability related to Microsoft cloud hardware. We are looking for an experienced engineer with a dedicated passion for customer focused solutions insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure.

We are looking for a Principal Design Verification Engineer - Formal to join the team.

#SCHIE #CSME

The candidate for this position will be expected and able to complete the following responsibilities upon hire:

• Own or lead Formal verification of Fabric Interconnect architectures IPs subsystems and reusable Fabric components from planning through signoff.
• Partner with architecture design and verification teams to define Formal verification strategies methodologies test plans and signoff criteria.
• Develop and enhance Formal verification environments assertions abstraction models checkers and reusable verification collateral.
• Drive root-cause analysis and closure of complex design and verification issues through Formal analysis simulation and debug.
• Improve verification productivity through automation methodologies and AI-assisted solutions.
• Coach and mentor engineers in Formal verification methodologies and best practices.
• Demonstrate Microsoft core values: Customer Focus Adaptability Collaboration Growth Mindset Drive for Results Influence for Impact Judgement and Diversity & Inclusion.

Required Qualifications:

• Doctorate in Electrical Engineering Computer Engineering Computer Science or related field AND 3 years technical engineering experience OR Masters Degree in Electrical Engineering Computer Engineering Computer Science or related field AND 6 years technical engineering experience OR Bachelors Degree in Electrical Engineering Computer Engineering Computer Science or related field AND 8 years technical engineering experience OR equivalent experience.

Screening Requirements

• Ability to meet Microsoft customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.
• This role will require access to information that is controlled for export under export control regulations potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations the EU Dual Use Regulation and/or other export control a condition of employment the successful candidate will be requiredto provide either proof of their country of citizenship or proof of their US. residency or other protected status(e.g. under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled meet this legal requirement and as a condition of employment the successful candidates citizenship will be verified with a valid passport. Lawful permanent residents refugees and asylees may verify status using other documents where applicable.

Preferred Qualifications:

• Doctorate in Electrical Engineering Computer Engineering Computer Science or related field AND 5 years technical engineering experience OR Masters Degree in Electrical Engineering Computer Engineering Computer Science or related field AND 8 years technical engineering experience OR Bachelors Degree in Electrical Engineering Computer Engineering Computer Science or related field AND 12 years technical engineering experience OR equivalent experience.
  1 year(s) experience working on or leading projects from beginning-to-end.
• 5 years of pre-silicon subsystem or IP Formal verification experience.
• Demonstrated expertise applying Formal verification methodologies to complex IPs subsystems SoCs or reusable library components.
• Demonstrated expertise in one or more of the following: Fabric Interconnects coherency CHI AMBA PCIe CXL protocol bridges virtualization security or memory subsystems.
• Experience driving verification from planning through signoff across multiple product cycles.
• Experience developing scalable Formal verification environments assertions assumptions checkers and reusable verification collateral.
• Experience solving complex cross-team technical challenges and driving verification closure.
• Working knowledge of simulation-based verification methodologies including System Verilog UVM assertions and coverage-driven verification.
• Proficiency with Python or similar scripting languages for automation and verification productivity.
• Experience applying AI-assisted tools to engineering and verification workflows

Silicon Engineering IC5 - The typical base pay range for this role across the U.S. is USD $142800 - $274800 per year. There is a different range applicable to specific work locations within the San Francisco Bay area and New York City metropolitan area and the base pay range for this role in those locations is USD $188000 - $304200 per year.

Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:
position will be open for a minimum of 5 days with applications accepted on an ongoing basis until the position is filled.

Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age ancestry citizenship color family or medical care leave gender identity or expression genetic information immigration status marital status medical condition national origin physical or mental disability political affiliation protected veteran or military status race ethnicity religion sex (including pregnancy) sexual orientation or any other characteristic protected by applicable local laws regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process read more about requesting accommodations.

Required Experience:

IC