Mechanical Engineering Manager

Our Purpose
TERADYNE where experience meets innovation and driving excellence in every connection. We are fueled by creativity and diversity of thought and in our workforce. Our employees are supportedto innovate and learn something new every day.

We cultivate a culture of inclusion for all employees that respects their individual strengths views and experiences. We believe that our differences enable us to be a better team one that makes better decisions drives innovation and delivers better business results.

Opportunity Overview
The Memory Test Division isseekingatechnically strong highly motivated Engineering Managerto lead a team focused oninterface development and signal deliveryforhighperformancememory test platforms. This teamis responsible fordesigning andoptimizingthe critical interconnects that enable clean reliablehighspeedsignaling to advanced memory devices.

This position is based inSan Jose CAoperatingwithin afastpacedmultisiteengineering environment. You will report tothe directorand collaborate closely with teams across signal integrity hardware design mechanical engineering and system architecture.

• Direct engineering activities related tomemorytestinterface hardware including load boards probe interfaces connectors cabling systems andother signal delivery.

• Manage department budgets staffing personnel development and recruitment for theinterface team.

• Lead a multidisciplinary team specializing in signal integrity interconnect designand validation materials and electromechanical integration

• Build and execute a roadmap for interface improvements aligned withmemorytestperformance reliability and manufacturability targets

• Establish KPIs for signal quality interface reliability andtestsystemperformance; report progress to senior leadership

• Collaborate with suppliers and external engineering partners todevelop signal delivery solutions and interconnect.

• Promote a culture of engineering rigorsignalintegrityawareness and continuous improvement across the Memory Test Division

All About You
You thrive in complex technical environments and are motivated by solvinghighspeedsignaling andinterfacearchitecturechallenges. You enjoy leading teams shaping technical direction and building robust hardware that supportsnextgenerationmemory devices.

• Bachelors degree inElectrical EngineeringMechanical Engineering or related field

• 8 years of experiencein electrical mechanical or electromechanical design within semiconductor equipment orhighspeedhardware systems

• Demonstratedexpertiseinsignal deliveryinterconnect designhighspeedrouting orinterface hardware development

• Strong background in design optimization materials evaluation and process improvements

• Proven ability to manage external design partners or contract engineering resources

• Excellent communication skillsoral written and presentation

• Broad technical fluency across hardware software mechanical thermal andsystemleveldomains

• Deep understanding of thedevelopmentlifecycleforelectromechanicalproducts

• Some travel overseas may berequired expect once per year.

We are only considering candidates local to position location and are unable to provide relocation for this position.

This position is not eligible for visa sponsorship.

Compensation:
The base salary range for this role is$16000 range is a good faith estimate and the amount of base salary will correspond with experience and skill set. This range can also fluctuate depending on demand and location.

Incentive Plan: This job is eligible for discretionary bonus(es) based on financial performance.

Benefits:

Teradyne offers a variety of robust health and well-being benefit programs including medical dental vision Flexible Spending Accounts retirement savings plans life and disability insurance paid vacation & holidays tuition assistance programs and more. Please click here to see details.

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