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Lead Principal IC Packaging Design Engineer

Best NanoTech


Job Location:

Chandler, TX - USA

Monthly Salary: Not provided by the employer
Posted: 30 June 2026 (30+ days ago)
Application Deadline: 27 September 2026
Vacancies: 1 Vacancy

Job Summary

Lead / Principal IC Packaging Design Engineer Location Work Mode & Experience

Location: Chandler Arizona OR Hillsboro Oregon (Onsite)

Employment: Long-Term Contract (12 Months)

Experience: 10 Years

Role Overview

We are seeking a Lead IC Packaging Design Engineer with extensive experience in advanced semiconductor package development. This role will lead package implementation guide complex substrate designs collaborate with architecture SI/PI manufacturing and reliability teams and drive high-quality package solutions from concept through production.

Key Responsibilities
  • Lead advanced semiconductor package design projects.
  • Drive complete package implementation using Siemens Xpedition or Cadence APD.
  • Define substrate architecture and layout strategy.
  • Lead SI/PI-aware package implementation.
  • Ensure package manufacturability yield and reliability.
  • Review package floorplans and routing methodologies.
  • Drive design rule compliance across projects.
  • Collaborate with architecture manufacturing and reliability teams.
  • Resolve complex package design challenges.
  • Mentor package design engineers.
  • Support customer reviews and technical discussions.
  • Contribute to package design process improvements and best practices.
Required Qualifications
  • Bachelors or Masters degree in Electrical/Electronics Engineering.
  • 10 years of IC Packaging Design experience.
  • Proven experience leading advanced package design programs.
  • Strong knowledge of package architecture substrate design and package implementation.
Technical Skills Package Design Platforms
  • Siemens Xpedition (Mentor Graphics XPD)
  • Cadence APD
  • Cadence Allegro
  • Cadence SiP
Advanced Semiconductor Packaging
  • Package Architecture
  • High-Density Substrate Design
  • Advanced Package Layout
  • Flip Chip
  • Multi-Chip Package Design
  • SiP Package Design
Design Engineering
  • Physical Package Design
  • SI/PI Optimization
  • Reliability Engineering
  • Yield Improvement
  • Design Rule Compliance
  • Design for Manufacturability (DFM)
Leadership
  • Technical Leadership
  • Design Reviews
  • Engineering Mentorship
  • Cross-functional Collaboration
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